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https://github.com/c64scene-ar/llvm-6502.git
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Add bunch of mem-whatever patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70726 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov
parent
2682bf5979
commit
01e0e8d119
@ -162,6 +162,35 @@ def ADD16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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[(set GR16:$dst, (add GR16:$src1, imm:$src2)),
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(implicit SRW)]>;
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let isTwoAddress = 0 in {
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def ADD8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
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"add.b\t{$src, $dst|$dst, $src}",
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[(store (add (load addr:$dst), GR8:$src), addr:$dst),
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(implicit SRW)]>;
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def ADD16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
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"add.w\t{$src, $dst|$dst, $src}",
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[(store (add (load addr:$dst), GR16:$src), addr:$dst),
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(implicit SRW)]>;
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def ADD8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
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"add.b\t{$src, $dst|$dst, $src}",
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[(store (add (load addr:$dst), (i8 imm:$src)), addr:$dst),
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(implicit SRW)]>;
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def ADD16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
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"add.w\t{$src, $dst|$dst, $src}",
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[(store (add (load addr:$dst), (i16 imm:$src)), addr:$dst),
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(implicit SRW)]>;
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def ADD8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
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"add.b\t{$src, $dst|$dst, $src}",
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[(store (add (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
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(implicit SRW)]>;
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def ADD16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
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"add.w\t{$src, $dst|$dst, $src}",
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[(store (add (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
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(implicit SRW)]>;
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}
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let Uses = [SRW] in {
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let isCommutable = 1 in { // X = ADDC Y, Z == X = ADDC Z, Y
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@ -192,8 +221,38 @@ def ADC16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
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"addc.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (adde GR16:$src1, (load addr:$src2))),
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(implicit SRW)]>;
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let isTwoAddress = 0 in {
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def ADC8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
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"addc.b\t{$src, $dst|$dst, $src}",
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[(store (adde (load addr:$dst), GR8:$src), addr:$dst),
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(implicit SRW)]>;
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def ADC16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
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"addc.w\t{$src, $dst|$dst, $src}",
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[(store (adde (load addr:$dst), GR16:$src), addr:$dst),
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(implicit SRW)]>;
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def ADC8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
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"addc.b\t{$src, $dst|$dst, $src}",
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[(store (adde (load addr:$dst), (i8 imm:$src)), addr:$dst),
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(implicit SRW)]>;
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def ADC16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
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"addc.w\t{$src, $dst|$dst, $src}",
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[(store (adde (load addr:$dst), (i16 imm:$src)), addr:$dst),
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(implicit SRW)]>;
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def ADC8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
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"addc.b\t{$src, $dst|$dst, $src}",
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[(store (adde (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
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(implicit SRW)]>;
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def ADC16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
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"addc.w\t{$src, $dst|$dst, $src}",
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[(store (adde (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
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(implicit SRW)]>;
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}
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} // Uses = [SRW]
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let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y
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def AND8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
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"and.b\t{$src2, $dst|$dst, $src2}",
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@ -223,6 +282,36 @@ def AND16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
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[(set GR16:$dst, (and GR16:$src1, (load addr:$src2))),
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(implicit SRW)]>;
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let isTwoAddress = 0 in {
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def AND8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
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"and.b\t{$src, $dst|$dst, $src}",
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[(store (and (load addr:$dst), GR8:$src), addr:$dst),
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(implicit SRW)]>;
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def AND16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
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"and.w\t{$src, $dst|$dst, $src}",
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[(store (and (load addr:$dst), GR16:$src), addr:$dst),
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(implicit SRW)]>;
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def AND8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
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"and.b\t{$src, $dst|$dst, $src}",
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[(store (and (load addr:$dst), (i8 imm:$src)), addr:$dst),
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(implicit SRW)]>;
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def AND16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
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"and.w\t{$src, $dst|$dst, $src}",
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[(store (and (load addr:$dst), (i16 imm:$src)), addr:$dst),
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(implicit SRW)]>;
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def AND8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
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"and.b\t{$src, $dst|$dst, $src}",
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[(store (and (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
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(implicit SRW)]>;
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def AND16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
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"and.w\t{$src, $dst|$dst, $src}",
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[(store (and (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
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(implicit SRW)]>;
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}
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let isCommutable = 1 in { // X = XOR Y, Z == X = XOR Z, Y
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def XOR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
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"xor.b\t{$src2, $dst|$dst, $src2}",
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@ -252,6 +341,36 @@ def XOR16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
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[(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
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(implicit SRW)]>;
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let isTwoAddress = 0 in {
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def XOR8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
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"xor.b\t{$src, $dst|$dst, $src}",
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[(store (xor (load addr:$dst), GR8:$src), addr:$dst),
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(implicit SRW)]>;
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def XOR16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
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"xor.w\t{$src, $dst|$dst, $src}",
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[(store (xor (load addr:$dst), GR16:$src), addr:$dst),
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(implicit SRW)]>;
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def XOR8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
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"xor.b\t{$src, $dst|$dst, $src}",
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[(store (xor (load addr:$dst), (i8 imm:$src)), addr:$dst),
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(implicit SRW)]>;
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def XOR16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
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"xor.w\t{$src, $dst|$dst, $src}",
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[(store (xor (load addr:$dst), (i16 imm:$src)), addr:$dst),
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(implicit SRW)]>;
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def XOR8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
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"xor.b\t{$src, $dst|$dst, $src}",
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[(store (xor (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
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(implicit SRW)]>;
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def XOR16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
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"xor.w\t{$src, $dst|$dst, $src}",
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[(store (xor (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
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(implicit SRW)]>;
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}
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def SUB8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
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"sub.b\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
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@ -279,6 +398,35 @@ def SUB16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
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[(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
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(implicit SRW)]>;
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let isTwoAddress = 0 in {
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def SUB8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
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"sub.b\t{$src, $dst|$dst, $src}",
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[(store (sub (load addr:$dst), GR8:$src), addr:$dst),
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(implicit SRW)]>;
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def SUB16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
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"sub.w\t{$src, $dst|$dst, $src}",
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[(store (sub (load addr:$dst), GR16:$src), addr:$dst),
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(implicit SRW)]>;
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def SUB8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
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"sub.b\t{$src, $dst|$dst, $src}",
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[(store (sub (load addr:$dst), (i8 imm:$src)), addr:$dst),
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(implicit SRW)]>;
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def SUB16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
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"sub.w\t{$src, $dst|$dst, $src}",
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[(store (sub (load addr:$dst), (i16 imm:$src)), addr:$dst),
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(implicit SRW)]>;
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def SUB8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
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"sub.b\t{$src, $dst|$dst, $src}",
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[(store (sub (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
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(implicit SRW)]>;
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def SUB16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
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"sub.w\t{$src, $dst|$dst, $src}",
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[(store (sub (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
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(implicit SRW)]>;
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}
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let Uses = [SRW] in {
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def SBC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
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"subc.b\t{$src2, $dst|$dst, $src2}",
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@ -306,8 +454,38 @@ def SBC16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
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"subc.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (sube GR16:$src1, (load addr:$src2))),
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(implicit SRW)]>;
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let isTwoAddress = 0 in {
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def SBC8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
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"subc.b\t{$src, $dst|$dst, $src}",
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[(store (sube (load addr:$dst), GR8:$src), addr:$dst),
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(implicit SRW)]>;
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def SBC16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
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"subc.w\t{$src, $dst|$dst, $src}",
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[(store (sube (load addr:$dst), GR16:$src), addr:$dst),
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(implicit SRW)]>;
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def SBC8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
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"subc.b\t{$src, $dst|$dst, $src}",
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[(store (sube (load addr:$dst), (i8 imm:$src)), addr:$dst),
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(implicit SRW)]>;
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def SBC16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
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"subc.w\t{$src, $dst|$dst, $src}",
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[(store (sube (load addr:$dst), (i16 imm:$src)), addr:$dst),
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(implicit SRW)]>;
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def SBC8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
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"subc.b\t{$src, $dst|$dst, $src}",
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[(store (sube (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
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(implicit SRW)]>;
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def SBC16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
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"subc.w\t{$src, $dst|$dst, $src}",
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[(store (sube (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
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(implicit SRW)]>;
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}
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} // Uses = [SRW]
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// FIXME: Provide proper encoding!
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def SAR16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
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"rra.w\t$dst",
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@ -319,6 +497,11 @@ def SEXT16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
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[(set GR16:$dst, (sext_inreg GR16:$src, i8)),
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(implicit SRW)]>;
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//def SEXT16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
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// "sxt\t$dst",
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// [(set GR16:$dst, (sext_inreg GR16:$src, i8)),
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// (implicit SRW)]>;
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} // Defs = [SRW]
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let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y
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@ -343,6 +526,36 @@ def OR8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
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def OR16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
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"bis.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>;
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let isTwoAddress = 0 in {
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def OR8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
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"bis.b\t{$src, $dst|$dst, $src}",
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[(store (or (load addr:$dst), GR8:$src), addr:$dst),
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(implicit SRW)]>;
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def OR16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
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"bis.w\t{$src, $dst|$dst, $src}",
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[(store (or (load addr:$dst), GR16:$src), addr:$dst),
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(implicit SRW)]>;
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def OR8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
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"bis.b\t{$src, $dst|$dst, $src}",
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[(store (or (load addr:$dst), (i8 imm:$src)), addr:$dst),
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(implicit SRW)]>;
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def OR16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
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"bis.w\t{$src, $dst|$dst, $src}",
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[(store (or (load addr:$dst), (i16 imm:$src)), addr:$dst),
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(implicit SRW)]>;
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def OR8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
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"bis.b\t{$src, $dst|$dst, $src}",
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[(store (or (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
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(implicit SRW)]>;
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def OR16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
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"bis.w\t{$src, $dst|$dst, $src}",
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[(store (or (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
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(implicit SRW)]>;
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}
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} // isTwoAddress = 1
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//===----------------------------------------------------------------------===//
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