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Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139422 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2011-09-09 22:24:36 +00:00
parent 46ac94ba8b
commit 08fef885eb
5 changed files with 39 additions and 3 deletions
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4
lib/Target/ARM/ARMInstrThumb2.td
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@ -1146,7 +1146,7 @@ class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
// assembler.
def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
(ins t2adrlabel:$addr, pred:$p),
IIC_iALUi, "adr{$p}.w\t$Rd, #$addr", []> {
IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []> {
let Inst{31-27} = 0b11110;
let Inst{25-24} = 0b10;
// Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
@ -1163,6 +1163,8 @@ def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
let Inst{26} = addr{11};
let Inst{14-12} = addr{10-8};
let Inst{7-0} = addr{7-0};
let DecoderMethod = "DecodeT2Adr";
}
let neverHasSideEffects = 1, isReMaterializable = 1 in

18
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -299,6 +299,8 @@ static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
#include "ARMGenDisassemblerTables.inc"
#include "ARMGenInstrInfo.inc"
@ -3762,3 +3764,19 @@ DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
return S;
}
static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn,
uint64_t Address, const void *Decoder) {
unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
if (sign1 != sign2) return MCDisassembler::Fail;
unsigned Val = fieldFromInstruction32(Insn, 0, 8);
Val |= fieldFromInstruction32(Insn, 12, 3) << 8;
Val |= fieldFromInstruction32(Insn, 26, 1) << 11;
Val |= sign1 << 12;
Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
return MCDisassembler::Success;
}

7
lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
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@ -662,7 +662,12 @@ getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
if (MO.isExpr())
return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
Fixups);
return MO.getImm();
int32_t Val = MO.getImm();
if (Val < 0) {
Val *= -1;
Val |= 0x1000;
}
return Val;
}
/// getAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label

6
test/MC/ARM/basic-thumb2-instructions.s
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@ -107,6 +107,12 @@ _func:
@ FIXME: ADR
@------------------------------------------------------------------------------
subw r11, pc, #3270
adr.w r11, #-826
@ CHECK: subw r11, pc, #3270 @ encoding: [0xaf,0xf6,0xc6,0x4b]
@ CHECK: adr.w r11, #-826 @ encoding: [0xaf,0xf2,0x3a,0x3b]
@------------------------------------------------------------------------------
@ AND (immediate)
@------------------------------------------------------------------------------

7
test/MC/Disassembler/ARM/thumb2.txt
View File

@ -88,8 +88,13 @@
#------------------------------------------------------------------------------
# FIXME: ADR
# ADR
#------------------------------------------------------------------------------
# CHECK: subw r11, pc, #3270
# CHECK: subw r11, pc, #826
0xaf 0xf6 0xc6 0x4b
0xaf 0xf2 0x3a 0x3b
#------------------------------------------------------------------------------
# AND (immediate)