mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-26 07:34:06 +00:00
First round of ppc long double. call/return and
basic arithmetic works. Rename RTLIB long double functions to distinguish different flavors of long double; the lib functions have different names, alas. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42644 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dale Johannesen
parent
b952d1f5be
commit
161e897b0f
@ -18,9 +18,8 @@
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namespace llvm {
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namespace RTLIB {
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/// RTLIB::Libcall enum - This enum defines all of the runtime library calls
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/// the backend can emit. "LD" is used for all long double types, since
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/// these functions will have the same interface on different targets even
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/// though the data is not in the same format.
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/// the backend can emit. The various long double types cannot be merged,
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/// because 80-bit library functions use "xf" and 128-bit use "tf".
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///
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enum Libcall {
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// Integer
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@ -46,22 +45,29 @@ namespace RTLIB {
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// FLOATING POINT
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ADD_F32,
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ADD_F64,
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ADD_PPCF128,
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SUB_F32,
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SUB_F64,
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SUB_PPCF128,
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MUL_F32,
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MUL_F64,
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MUL_PPCF128,
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DIV_F32,
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DIV_F64,
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DIV_PPCF128,
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REM_F32,
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REM_F64,
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REM_PPCF128,
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NEG_F32,
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NEG_F64,
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POWI_F32,
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POWI_F64,
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POWI_LD,
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POWI_F80,
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POWI_PPCF128,
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SQRT_F32,
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SQRT_F64,
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SQRT_LD,
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SQRT_F80,
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SQRT_PPCF128,
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SIN_F32,
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SIN_F64,
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COS_F32,
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@ -74,18 +80,21 @@ namespace RTLIB {
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FPTOSINT_F32_I64,
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FPTOSINT_F64_I32,
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FPTOSINT_F64_I64,
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FPTOSINT_LD_I64,
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FPTOSINT_F80_I64,
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FPTOSINT_PPCF128_I64,
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FPTOUINT_F32_I32,
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FPTOUINT_F32_I64,
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FPTOUINT_F64_I32,
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FPTOUINT_F64_I64,
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FPTOUINT_LD_I32,
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FPTOUINT_LD_I64,
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FPTOUINT_F80_I32,
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FPTOUINT_F80_I64,
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FPTOUINT_PPCF128_I64,
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SINTTOFP_I32_F32,
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SINTTOFP_I32_F64,
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SINTTOFP_I64_F32,
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SINTTOFP_I64_F64,
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SINTTOFP_I64_LD,
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SINTTOFP_I64_F80,
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SINTTOFP_I64_PPCF128,
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UINTTOFP_I32_F32,
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UINTTOFP_I32_F64,
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UINTTOFP_I64_F32,
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@ -3055,7 +3055,10 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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switch(Node->getOpcode()) {
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case ISD::FSQRT:
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LC = VT == MVT::f32 ? RTLIB::SQRT_F32 :
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VT == MVT::f64 ? RTLIB::SQRT_F64 : RTLIB::SQRT_LD;
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VT == MVT::f64 ? RTLIB::SQRT_F64 :
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VT == MVT::f80 ? RTLIB::SQRT_F80 :
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VT == MVT::ppcf128 ? RTLIB::SQRT_PPCF128 :
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RTLIB::UNKNOWN_LIBCALL;
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break;
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case ISD::FSIN:
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LC = VT == MVT::f32 ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
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@ -3079,7 +3082,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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RTLIB::Libcall LC =
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Node->getValueType(0) == MVT::f32 ? RTLIB::POWI_F32 :
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Node->getValueType(0) == MVT::f64 ? RTLIB::POWI_F64 :
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RTLIB::POWI_LD;
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Node->getValueType(0) == MVT::f80 ? RTLIB::POWI_F80 :
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Node->getValueType(0) == MVT::ppcf128 ? RTLIB::POWI_PPCF128 :
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RTLIB::UNKNOWN_LIBCALL;
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SDOperand Dummy;
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Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
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false/*sign irrelevant*/, Dummy);
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@ -3261,9 +3266,13 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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else if (OVT == MVT::f64)
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LC = (VT == MVT::i32)
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? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
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else if (OVT == MVT::f80 || OVT == MVT::f128 || OVT == MVT::ppcf128) {
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else if (OVT == MVT::f80) {
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assert(VT == MVT::i64);
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LC = RTLIB::FPTOSINT_LD_I64;
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LC = RTLIB::FPTOSINT_F80_I64;
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}
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else if (OVT == MVT::ppcf128) {
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assert(VT == MVT::i64);
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LC = RTLIB::FPTOSINT_PPCF128_I64;
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}
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break;
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}
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@ -3275,9 +3284,13 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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else if (OVT == MVT::f64)
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LC = (VT == MVT::i32)
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? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
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else if (OVT == MVT::f80 || OVT == MVT::f128 || OVT == MVT::ppcf128) {
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else if (OVT == MVT::f80) {
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LC = (VT == MVT::i32)
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? RTLIB::FPTOUINT_LD_I32 : RTLIB::FPTOUINT_LD_I64;
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? RTLIB::FPTOUINT_F80_I32 : RTLIB::FPTOUINT_F80_I64;
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}
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else if (OVT == MVT::ppcf128) {
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assert(VT == MVT::i64);
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LC = RTLIB::FPTOUINT_PPCF128_I64;
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}
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break;
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}
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@ -5375,13 +5388,15 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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}
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}
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RTLIB::Libcall LC;
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RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
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if (Node->getOperand(0).getValueType() == MVT::f32)
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LC = RTLIB::FPTOSINT_F32_I64;
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else if (Node->getOperand(0).getValueType() == MVT::f64)
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LC = RTLIB::FPTOSINT_F64_I64;
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else
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LC = RTLIB::FPTOSINT_LD_I64;
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else if (Node->getOperand(0).getValueType() == MVT::f80)
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LC = RTLIB::FPTOSINT_F80_I64;
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else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
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LC = RTLIB::FPTOSINT_PPCF128_I64;
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Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
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false/*sign irrelevant*/, Hi);
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break;
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@ -5410,10 +5425,10 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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LC = RTLIB::FPTOUINT_F32_I64;
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else if (Node->getOperand(0).getValueType() == MVT::f64)
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LC = RTLIB::FPTOUINT_F64_I64;
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else if (Node->getOperand(0).getValueType() == MVT::f80 ||
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Node->getOperand(0).getValueType() == MVT::f128 ||
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Node->getOperand(0).getValueType() == MVT::ppcf128)
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LC = RTLIB::FPTOUINT_LD_I64;
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else if (Node->getOperand(0).getValueType() == MVT::f80)
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LC = RTLIB::FPTOUINT_F80_I64;
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else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
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LC = RTLIB::FPTOUINT_PPCF128_I64;
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Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
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false/*sign irrelevant*/, Hi);
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break;
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@ -5679,23 +5694,35 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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break;
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case ISD::FADD:
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Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
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? RTLIB::ADD_F32 : RTLIB::ADD_F64),
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Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::ADD_F32 :
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VT == MVT::f64 ? RTLIB::ADD_F64 :
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VT == MVT::ppcf128 ?
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RTLIB::ADD_PPCF128 :
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RTLIB::UNKNOWN_LIBCALL),
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Node, false, Hi);
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break;
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case ISD::FSUB:
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Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
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? RTLIB::SUB_F32 : RTLIB::SUB_F64),
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Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::SUB_F32 :
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VT == MVT::f64 ? RTLIB::SUB_F64 :
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VT == MVT::ppcf128 ?
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RTLIB::SUB_PPCF128 :
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RTLIB::UNKNOWN_LIBCALL),
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Node, false, Hi);
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break;
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case ISD::FMUL:
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Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
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? RTLIB::MUL_F32 : RTLIB::MUL_F64),
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Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::MUL_F32 :
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VT == MVT::f64 ? RTLIB::MUL_F64 :
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VT == MVT::ppcf128 ?
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RTLIB::MUL_PPCF128 :
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RTLIB::UNKNOWN_LIBCALL),
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Node, false, Hi);
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break;
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case ISD::FDIV:
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Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
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? RTLIB::DIV_F32 : RTLIB::DIV_F64),
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Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::DIV_F32 :
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VT == MVT::f64 ? RTLIB::DIV_F64 :
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VT == MVT::ppcf128 ?
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RTLIB::DIV_PPCF128 :
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RTLIB::UNKNOWN_LIBCALL),
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Node, false, Hi);
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break;
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case ISD::FP_EXTEND:
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@ -5707,7 +5734,10 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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case ISD::FPOWI:
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Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) ? RTLIB::POWI_F32 :
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(VT == MVT::f64) ? RTLIB::POWI_F64 :
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RTLIB::POWI_LD),
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(VT == MVT::f80) ? RTLIB::POWI_F80 :
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(VT == MVT::ppcf128) ?
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RTLIB::POWI_PPCF128 :
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RTLIB::UNKNOWN_LIBCALL),
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Node, false, Hi);
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break;
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case ISD::FSQRT:
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@ -5717,7 +5747,10 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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switch(Node->getOpcode()) {
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case ISD::FSQRT:
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LC = (VT == MVT::f32) ? RTLIB::SQRT_F32 :
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(VT == MVT::f64) ? RTLIB::SQRT_F64 : RTLIB::SQRT_LD;
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(VT == MVT::f64) ? RTLIB::SQRT_F64 :
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(VT == MVT::f80) ? RTLIB::SQRT_F80 :
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(VT == MVT::ppcf128) ? RTLIB::SQRT_PPCF128 :
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RTLIB::UNKNOWN_LIBCALL;
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break;
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case ISD::FSIN:
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LC = (VT == MVT::f32) ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
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@ -5768,9 +5801,13 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32;
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else if (VT == MVT::f64)
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LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64;
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else if (VT == MVT::f80 || VT == MVT::f128 || VT == MVT::ppcf128) {
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else if (VT == MVT::f80) {
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assert(isSigned);
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LC = RTLIB::SINTTOFP_I64_LD;
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LC = RTLIB::SINTTOFP_I64_F80;
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}
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else if (VT == MVT::ppcf128) {
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assert(isSigned);
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LC = RTLIB::SINTTOFP_I64_PPCF128;
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}
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} else {
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if (VT == MVT::f32)
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@ -46,22 +46,29 @@ static void InitLibcallNames(const char **Names) {
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Names[RTLIB::NEG_I64] = "__negdi2";
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Names[RTLIB::ADD_F32] = "__addsf3";
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Names[RTLIB::ADD_F64] = "__adddf3";
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Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
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Names[RTLIB::SUB_F32] = "__subsf3";
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Names[RTLIB::SUB_F64] = "__subdf3";
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Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
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Names[RTLIB::MUL_F32] = "__mulsf3";
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Names[RTLIB::MUL_F64] = "__muldf3";
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Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
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Names[RTLIB::DIV_F32] = "__divsf3";
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Names[RTLIB::DIV_F64] = "__divdf3";
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Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
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Names[RTLIB::REM_F32] = "fmodf";
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Names[RTLIB::REM_F64] = "fmod";
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Names[RTLIB::REM_PPCF128] = "fmodl";
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Names[RTLIB::NEG_F32] = "__negsf2";
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Names[RTLIB::NEG_F64] = "__negdf2";
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Names[RTLIB::POWI_F32] = "__powisf2";
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Names[RTLIB::POWI_F64] = "__powidf2";
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Names[RTLIB::POWI_LD] = "__powixf2";
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Names[RTLIB::POWI_F80] = "__powixf2";
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Names[RTLIB::POWI_PPCF128] = "__powitf2";
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Names[RTLIB::SQRT_F32] = "sqrtf";
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Names[RTLIB::SQRT_F64] = "sqrt";
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Names[RTLIB::SQRT_LD] = "sqrtl";
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Names[RTLIB::SQRT_F80] = "sqrtl";
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Names[RTLIB::SQRT_PPCF128] = "sqrtl";
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Names[RTLIB::SIN_F32] = "sinf";
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Names[RTLIB::SIN_F64] = "sin";
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Names[RTLIB::COS_F32] = "cosf";
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@ -72,18 +79,21 @@ static void InitLibcallNames(const char **Names) {
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Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
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Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
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Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
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Names[RTLIB::FPTOSINT_LD_I64] = "__fixxfdi";
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Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
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Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
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Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
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Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
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Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
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Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
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Names[RTLIB::FPTOUINT_LD_I32] = "__fixunsxfsi";
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Names[RTLIB::FPTOUINT_LD_I64] = "__fixunsxfdi";
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Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
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Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
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Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
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Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
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Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
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Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
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Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
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Names[RTLIB::SINTTOFP_I64_LD] = "__floatdixf";
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Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
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Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
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Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
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Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
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Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
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@ -222,6 +232,14 @@ void TargetLowering::computeRegisterProperties() {
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}
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}
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// ppcf128 type is really two f64's.
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if (!isTypeLegal(MVT::ppcf128)) {
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NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
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RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
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TransformToType[MVT::ppcf128] = MVT::f64;
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ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
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}
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// Decide how to handle f64. If the target does not have native f64 support,
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// expand it to i64 and we will be generating soft float library calls.
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if (!isTypeLegal(MVT::f64)) {
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@ -25,7 +25,8 @@ def RetCC_PPC : CallingConv<[
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CCIfType<[i32], CCAssignToReg<[R3, R4]>>,
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CCIfType<[i64], CCAssignToReg<[X3, X4]>>,
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CCIfType<[f32, f64], CCAssignToReg<[F1]>>,
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CCIfType<[f32], CCAssignToReg<[F1]>>,
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CCIfType<[f64], CCAssignToReg<[F1, F2]>>,
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// Vector types are always returned in V2.
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CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToReg<[V2]>>
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@ -1812,8 +1812,20 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG,
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NumResults = 1;
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NodeTys.push_back(MVT::i64);
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break;
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case MVT::f32:
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case MVT::f64:
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if (Op.Val->getValueType(1) == MVT::f64) {
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Chain = DAG.getCopyFromReg(Chain, PPC::F1, MVT::f64, InFlag).getValue(1);
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ResultVals[0] = Chain.getValue(0);
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Chain = DAG.getCopyFromReg(Chain, PPC::F2, MVT::f64,
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Chain.getValue(2)).getValue(1);
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ResultVals[1] = Chain.getValue(0);
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NumResults = 2;
|
||||
NodeTys.push_back(MVT::f64);
|
||||
NodeTys.push_back(MVT::f64);
|
||||
break;
|
||||
}
|
||||
// else fall through
|
||||
case MVT::f32:
|
||||
Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0),
|
||||
InFlag).getValue(1);
|
||||
ResultVals[0] = Chain.getValue(0);
|
||||
|
||||
29
test/CodeGen/PowerPC/ppcf128-1-opt.ll
Normal file
29
test/CodeGen/PowerPC/ppcf128-1-opt.ll
Normal file
@ -0,0 +1,29 @@
|
||||
; RUN: llvm-as < %s | llc > %t
|
||||
; ModuleID = '<stdin>'
|
||||
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
|
||||
target triple = "powerpc-apple-darwin8"
|
||||
|
||||
define ppc_fp128 @plus(ppc_fp128 %x, ppc_fp128 %y) {
|
||||
entry:
|
||||
%tmp3 = add ppc_fp128 %x, %y ; <ppc_fp128> [#uses=1]
|
||||
ret ppc_fp128 %tmp3
|
||||
}
|
||||
|
||||
define ppc_fp128 @minus(ppc_fp128 %x, ppc_fp128 %y) {
|
||||
entry:
|
||||
%tmp3 = sub ppc_fp128 %x, %y ; <ppc_fp128> [#uses=1]
|
||||
ret ppc_fp128 %tmp3
|
||||
}
|
||||
|
||||
define ppc_fp128 @times(ppc_fp128 %x, ppc_fp128 %y) {
|
||||
entry:
|
||||
%tmp3 = mul ppc_fp128 %x, %y ; <ppc_fp128> [#uses=1]
|
||||
ret ppc_fp128 %tmp3
|
||||
}
|
||||
|
||||
define ppc_fp128 @divide(ppc_fp128 %x, ppc_fp128 %y) {
|
||||
entry:
|
||||
%tmp3 = fdiv ppc_fp128 %x, %y ; <ppc_fp128> [#uses=1]
|
||||
ret ppc_fp128 %tmp3
|
||||
}
|
||||
|
||||
92
test/CodeGen/PowerPC/ppcf128-1.ll
Normal file
92
test/CodeGen/PowerPC/ppcf128-1.ll
Normal file
@ -0,0 +1,92 @@
|
||||
; RUN: llvm-as < %s | opt -std-compile-opts | llc > %t
|
||||
; ModuleID = 'ld3.c'
|
||||
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
|
||||
target triple = "powerpc-apple-darwin8"
|
||||
|
||||
define ppc_fp128 @plus(ppc_fp128 %x, ppc_fp128 %y) {
|
||||
entry:
|
||||
%x_addr = alloca ppc_fp128 ; <ppc_fp128*> [#uses=2]
|
||||
%y_addr = alloca ppc_fp128 ; <ppc_fp128*> [#uses=2]
|
||||
%retval = alloca ppc_fp128, align 16 ; <ppc_fp128*> [#uses=2]
|
||||
%tmp = alloca ppc_fp128, align 16 ; <ppc_fp128*> [#uses=2]
|
||||
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
|
||||
store ppc_fp128 %x, ppc_fp128* %x_addr
|
||||
store ppc_fp128 %y, ppc_fp128* %y_addr
|
||||
%tmp1 = load ppc_fp128* %x_addr, align 16 ; <ppc_fp128> [#uses=1]
|
||||
%tmp2 = load ppc_fp128* %y_addr, align 16 ; <ppc_fp128> [#uses=1]
|
||||
%tmp3 = add ppc_fp128 %tmp1, %tmp2 ; <ppc_fp128> [#uses=1]
|
||||
store ppc_fp128 %tmp3, ppc_fp128* %tmp, align 16
|
||||
%tmp4 = load ppc_fp128* %tmp, align 16 ; <ppc_fp128> [#uses=1]
|
||||
store ppc_fp128 %tmp4, ppc_fp128* %retval, align 16
|
||||
br label %return
|
||||
|
||||
return: ; preds = %entry
|
||||
%retval5 = load ppc_fp128* %retval ; <ppc_fp128> [#uses=1]
|
||||
ret ppc_fp128 %retval5
|
||||
}
|
||||
|
||||
define ppc_fp128 @minus(ppc_fp128 %x, ppc_fp128 %y) {
|
||||
entry:
|
||||
%x_addr = alloca ppc_fp128 ; <ppc_fp128*> [#uses=2]
|
||||
%y_addr = alloca ppc_fp128 ; <ppc_fp128*> [#uses=2]
|
||||
%retval = alloca ppc_fp128, align 16 ; <ppc_fp128*> [#uses=2]
|
||||
%tmp = alloca ppc_fp128, align 16 ; <ppc_fp128*> [#uses=2]
|
||||
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
|
||||
store ppc_fp128 %x, ppc_fp128* %x_addr
|
||||
store ppc_fp128 %y, ppc_fp128* %y_addr
|
||||
%tmp1 = load ppc_fp128* %x_addr, align 16 ; <ppc_fp128> [#uses=1]
|
||||
%tmp2 = load ppc_fp128* %y_addr, align 16 ; <ppc_fp128> [#uses=1]
|
||||
%tmp3 = sub ppc_fp128 %tmp1, %tmp2 ; <ppc_fp128> [#uses=1]
|
||||
store ppc_fp128 %tmp3, ppc_fp128* %tmp, align 16
|
||||
%tmp4 = load ppc_fp128* %tmp, align 16 ; <ppc_fp128> [#uses=1]
|
||||
store ppc_fp128 %tmp4, ppc_fp128* %retval, align 16
|
||||
br label %return
|
||||
|
||||
return: ; preds = %entry
|
||||
%retval5 = load ppc_fp128* %retval ; <ppc_fp128> [#uses=1]
|
||||
ret ppc_fp128 %retval5
|
||||
}
|
||||
|
||||
define ppc_fp128 @times(ppc_fp128 %x, ppc_fp128 %y) {
|
||||
entry:
|
||||
%x_addr = alloca ppc_fp128 ; <ppc_fp128*> [#uses=2]
|
||||
%y_addr = alloca ppc_fp128 ; <ppc_fp128*> [#uses=2]
|
||||
%retval = alloca ppc_fp128, align 16 ; <ppc_fp128*> [#uses=2]
|
||||
%tmp = alloca ppc_fp128, align 16 ; <ppc_fp128*> [#uses=2]
|
||||
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
|
||||
store ppc_fp128 %x, ppc_fp128* %x_addr
|
||||
store ppc_fp128 %y, ppc_fp128* %y_addr
|
||||
%tmp1 = load ppc_fp128* %x_addr, align 16 ; <ppc_fp128> [#uses=1]
|
||||
%tmp2 = load ppc_fp128* %y_addr, align 16 ; <ppc_fp128> [#uses=1]
|
||||
%tmp3 = mul ppc_fp128 %tmp1, %tmp2 ; <ppc_fp128> [#uses=1]
|
||||
store ppc_fp128 %tmp3, ppc_fp128* %tmp, align 16
|
||||
%tmp4 = load ppc_fp128* %tmp, align 16 ; <ppc_fp128> [#uses=1]
|
||||
store ppc_fp128 %tmp4, ppc_fp128* %retval, align 16
|
||||
br label %return
|
||||
|
||||
return: ; preds = %entry
|
||||
%retval5 = load ppc_fp128* %retval ; <ppc_fp128> [#uses=1]
|
||||
ret ppc_fp128 %retval5
|
||||
}
|
||||
|
||||
define ppc_fp128 @divide(ppc_fp128 %x, ppc_fp128 %y) {
|
||||
entry:
|
||||
%x_addr = alloca ppc_fp128 ; <ppc_fp128*> [#uses=2]
|
||||
%y_addr = alloca ppc_fp128 ; <ppc_fp128*> [#uses=2]
|
||||
%retval = alloca ppc_fp128, align 16 ; <ppc_fp128*> [#uses=2]
|
||||
%tmp = alloca ppc_fp128, align 16 ; <ppc_fp128*> [#uses=2]
|
||||
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
|
||||
store ppc_fp128 %x, ppc_fp128* %x_addr
|
||||
store ppc_fp128 %y, ppc_fp128* %y_addr
|
||||
%tmp1 = load ppc_fp128* %x_addr, align 16 ; <ppc_fp128> [#uses=1]
|
||||
%tmp2 = load ppc_fp128* %y_addr, align 16 ; <ppc_fp128> [#uses=1]
|
||||
%tmp3 = fdiv ppc_fp128 %tmp1, %tmp2 ; <ppc_fp128> [#uses=1]
|
||||
store ppc_fp128 %tmp3, ppc_fp128* %tmp, align 16
|
||||
%tmp4 = load ppc_fp128* %tmp, align 16 ; <ppc_fp128> [#uses=1]
|
||||
store ppc_fp128 %tmp4, ppc_fp128* %retval, align 16
|
||||
br label %return
|
||||
|
||||
return: ; preds = %entry
|
||||
%retval5 = load ppc_fp128* %retval ; <ppc_fp128> [#uses=1]
|
||||
ret ppc_fp128 %retval5
|
||||
}
|
||||
Loading…
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Reference in New Issue
Block a user