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Rename ARM instruction formats NEONGetLnFrm, NEONSetLnFrm and NEONDupFrm to

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"N..." instead of "NEON..." for consistency with the other NEON format names.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106921 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2010-06-25 23:56:05 +00:00
parent bdffc16d65
commit 184723d9be
3 changed files with 27 additions and 27 deletions
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6
lib/Target/ARM/ARMBaseInstrInfo.h
View File

@ -120,9 +120,9 @@ namespace ARMII {
MiscFrm = 25 << FormShift,
// NEON formats
NEONGetLnFrm = 26 << FormShift,
NEONSetLnFrm = 27 << FormShift,
NEONDupFrm = 28 << FormShift,
NGetLnFrm = 26 << FormShift,
NSetLnFrm = 27 << FormShift,
NDupFrm = 28 << FormShift,
NLdStFrm = 31 << FormShift,
N1RegModImmFrm= 32 << FormShift,
N2RegFrm = 33 << FormShift,

36
lib/Target/ARM/ARMInstrFormats.td
View File

@ -52,21 +52,21 @@ def VFPMiscFrm : Format<23>;
def ThumbFrm : Format<24>;
def MiscFrm : Format<25>;
def NEONGetLnFrm : Format<26>;
def NEONSetLnFrm : Format<27>;
def NEONDupFrm : Format<28>;
def NLdStFrm : Format<31>;
def N1RegModImmFrm : Format<32>;
def N2RegFrm : Format<33>;
def NVCVTFrm : Format<34>;
def NVDupLnFrm : Format<35>;
def N2RegVShLFrm : Format<36>;
def N2RegVShRFrm : Format<37>;
def N3RegFrm : Format<38>;
def N3RegVShFrm : Format<39>;
def NVExtFrm : Format<40>;
def NVMulSLFrm : Format<41>;
def NVTBLFrm : Format<42>;
def NGetLnFrm : Format<26>;
def NSetLnFrm : Format<27>;
def NDupFrm : Format<28>;
def NLdStFrm : Format<31>;
def N1RegModImmFrm: Format<32>;
def N2RegFrm : Format<33>;
def NVCVTFrm : Format<34>;
def NVDupLnFrm : Format<35>;
def N2RegVShLFrm : Format<36>;
def N2RegVShRFrm : Format<37>;
def N3RegFrm : Format<38>;
def N3RegVShFrm : Format<39>;
def NVExtFrm : Format<40>;
def NVMulSLFrm : Format<41>;
def NVTBLFrm : Format<42>;
// Misc flags.
@ -1649,17 +1649,17 @@ class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
dag oops, dag iops, InstrItinClass itin,
string opc, string dt, string asm, list<dag> pattern>
: NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONGetLnFrm, itin,
: NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin,
opc, dt, asm, pattern>;
class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
dag oops, dag iops, InstrItinClass itin,
string opc, string dt, string asm, list<dag> pattern>
: NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONSetLnFrm, itin,
: NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin,
opc, dt, asm, pattern>;
class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
dag oops, dag iops, InstrItinClass itin,
string opc, string dt, string asm, list<dag> pattern>
: NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONDupFrm, itin,
: NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin,
opc, dt, asm, pattern>;
// Vector Duplicate Lane (from scalar to all elements)

12
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
View File

@ -2841,7 +2841,7 @@ static bool DisassembleNVTBLFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
// Vector Get Lane (move scalar to ARM core register) Instructions.
// VGETLNi32, VGETLNs16, VGETLNs8, VGETLNu16, VGETLNu8: Rt Dn index
static bool DisassembleNEONGetLnFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
static bool DisassembleNGetLnFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
const TargetInstrDesc &TID = ARMInsts[Opcode];
@ -2875,7 +2875,7 @@ static bool DisassembleNEONGetLnFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
// Vector Set Lane (move ARM core register to scalar) Instructions.
// VSETLNi16, VSETLNi32, VSETLNi8: Dd Dd (TIED_TO) Rt index
static bool DisassembleNEONSetLnFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
static bool DisassembleNSetLnFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
const TargetInstrDesc &TID = ARMInsts[Opcode];
@ -2914,7 +2914,7 @@ static bool DisassembleNEONSetLnFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
// Vector Duplicate Instructions (from ARM core register to all elements).
// VDUP8d, VDUP16d, VDUP32d, VDUP8q, VDUP16q, VDUP32q: Qd/Dd Rt
static bool DisassembleNEONDupFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
static bool DisassembleNDupFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
@ -3086,9 +3086,9 @@ static const DisassembleFP FuncPtrs[] = {
&DisassembleVFPMiscFrm,
&DisassembleThumbFrm,
&DisassembleMiscFrm,
&DisassembleNEONGetLnFrm,
&DisassembleNEONSetLnFrm,
&DisassembleNEONDupFrm,
&DisassembleNGetLnFrm,
&DisassembleNSetLnFrm,
&DisassembleNDupFrm,
0,
0,