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Emit neg.s or neg.d only if -enable-no-nans-fp-math is supplied by user,
otherwise expand FNEG during legalization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154546 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -190,9 +190,10 @@ let Predicates = [IsFP64bit] in {
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def CVT_D64_L : FFR1<0x21, 21, "cvt", "d.l", FGR64, FGR64>;
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}
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let Predicates = [NoNaNsFPMath] in
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defm FABS : FFR1P_M<0x5, "abs", fabs>;
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defm FNEG : FFR1P_M<0x7, "neg", fneg>;
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let Predicates = [NoNaNsFPMath] in {
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defm FABS : FFR1P_M<0x5, "abs", fabs>;
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defm FNEG : FFR1P_M<0x7, "neg", fneg>;
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}
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defm FSQRT : FFR1P_M<0x4, "sqrt", fsqrt>;
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// The odd-numbered registers are only referenced when doing loads,
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