6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-19 19:29:31 +00:00
Code Issues Projects Releases Wiki Activity

Add a bunch more instructions

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12737 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2004-04-07 04:06:46 +00:00
parent f97b31e9cf
commit 22ede709f6
6 changed files with 200 additions and 104 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

66
lib/Target/Sparc/InstSelectSimple.cpp
View File

@ -288,33 +288,53 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) {
unsigned Op1Reg = getReg (I.getOperand (1));
unsigned ResultReg = makeAnotherReg (I.getType ());
unsigned OpCase = ~0;
// FIXME: support long, ulong, fp.
switch (I.getOpcode ()) {
case Instruction::Add:
BuildMI (BB, V8::ADDrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
break;
case Instruction::Sub:
BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
break;
case Instruction::Mul: {
unsigned Opcode = I.getType ()->isSigned () ? V8::SMULrr : V8::UMULrr;
BuildMI (BB, Opcode, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
break;
case Instruction::Add: OpCase = 0; break;
case Instruction::Sub: OpCase = 1; break;
case Instruction::Mul: OpCase = 2; break;
case Instruction::And: OpCase = 3; break;
case Instruction::Or: OpCase = 4; break;
case Instruction::Xor: OpCase = 5; break;
case Instruction::Div:
case Instruction::Rem: {
unsigned Dest = ResultReg;
if (I.getOpcode() == Instruction::Rem)
Dest = makeAnotherReg(I.getType());
// FIXME: this is probably only right for 32 bit operands.
if (I.getType ()->isSigned()) {
unsigned Tmp = makeAnotherReg (I.getType ());
// Sign extend into the Y register
BuildMI (BB, V8::SRAri, 2, Tmp).addReg (Op0Reg).addZImm (31);
BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (Tmp).addReg (V8::G0);
BuildMI (BB, V8::SDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
} else {
// Zero extend into the Y register, ie, just set it to zero
BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
BuildMI (BB, V8::UDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
}
case Instruction::Div: {
unsigned Opcode = I.getType ()->isSigned () ? V8::SDIVrr : V8::UDIVrr;
// Clear out the Y register (top half of LHS of divide)
BuildMI (BB, V8::WRYrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
BuildMI (BB, V8::NOP, 0); // WR may take up to 4 cycles to finish
BuildMI (BB, V8::NOP, 0);
BuildMI (BB, V8::NOP, 0);
BuildMI (BB, Opcode, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
break;
if (I.getOpcode() == Instruction::Rem) {
unsigned Tmp = makeAnotherReg (I.getType ());
BuildMI (BB, V8::SMULrr, 2, Tmp).addReg(Dest).addReg(Op1Reg);
BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg(Op0Reg).addReg(Tmp);
}
default:
visitInstruction (I);
return;
break;
}
default:
visitInstruction (I);
return;
}
if (OpCase != ~0U) {
static const unsigned Opcodes[] = {
V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr
};
BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
}
switch (getClass (I.getType ())) {

20
lib/Target/Sparc/SparcInstrInfo.td
View File

@ -75,9 +75,12 @@ let rd = 0, imm = 0 in
def NOP : F2_1<0b100, "nop">;
// Section B.11 - Logical Instructions, p. 106
def ANDrr : F3_1<2, 0b000001, "and">;
def ANDri : F3_2<2, 0b000001, "and">;
def ORrr : F3_1<2, 0b000010, "or">;
def ORri : F3_2<2, 0b000010, "or">;
def XORrr : F3_1<2, 0b000011, "xor">;
def XORri : F3_2<2, 0b000011, "xor">;
// Section B.12 - Shift Instructions, p. 107
def SLLri : F3_1<2, 0b100101, "sll">;
@ -95,8 +98,14 @@ def UMULrr : F3_1<2, 0b001010, "umul">;
def SMULrr : F3_1<2, 0b001011, "smul">;
// Section B.19 - Divide Instructions, p. 115
def UDIVrr: F3_1<2, 0b001110, "udiv">;
def SDIVrr: F3_1<2, 0b001111, "sdiv">;
def UDIVrr : F3_1<2, 0b001110, "udiv">;
def UDIVri : F3_2<2, 0b001110, "udiv">;
def SDIVrr : F3_1<2, 0b001111, "sdiv">;
def SDIVri : F3_2<2, 0b001111, "sdiv">;
def UDIVCCrr : F3_1<2, 0b011110, "udivcc">;
def UDIVCCri : F3_2<2, 0b011110, "udivcc">;
def SDIVCCrr : F3_1<2, 0b011111, "sdivcc">;
def SDIVCCri : F3_2<2, 0b011111, "sdivcc">;
// Section B.20 - SAVE and RESTORE, p. 117
def SAVErr : F3_1<2, 0b111100, "save">; // save r, r, r
@ -118,7 +127,6 @@ def CALL : InstV8 {
def JMPLrr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
def JMPLri : F3_2<2, 0b111000, "jmpl">; // jmpl [rs1+imm], rd
// Section B.29 - Write State Register Instructions, p. 133
let rd = 0 in
def WRYrr : F3_1<2, 0b110000, "wr">; // Special case of WRASR
def WRASRrr : F3_1<2, 0b110000, "wr">; // Special reg = reg ^ reg
// Section B.29 - Write State Register Instructions
def WRrr : F3_1<2, 0b110000, "wr">; // wr rs1, rs2, rd
def WRri : F3_2<2, 0b110000, "wr">; // wr rs1, imm, rd

66
lib/Target/Sparc/SparcV8ISelSimple.cpp
View File

@ -288,33 +288,53 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) {
unsigned Op1Reg = getReg (I.getOperand (1));
unsigned ResultReg = makeAnotherReg (I.getType ());
unsigned OpCase = ~0;
// FIXME: support long, ulong, fp.
switch (I.getOpcode ()) {
case Instruction::Add:
BuildMI (BB, V8::ADDrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
break;
case Instruction::Sub:
BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
break;
case Instruction::Mul: {
unsigned Opcode = I.getType ()->isSigned () ? V8::SMULrr : V8::UMULrr;
BuildMI (BB, Opcode, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
break;
case Instruction::Add: OpCase = 0; break;
case Instruction::Sub: OpCase = 1; break;
case Instruction::Mul: OpCase = 2; break;
case Instruction::And: OpCase = 3; break;
case Instruction::Or: OpCase = 4; break;
case Instruction::Xor: OpCase = 5; break;
case Instruction::Div:
case Instruction::Rem: {
unsigned Dest = ResultReg;
if (I.getOpcode() == Instruction::Rem)
Dest = makeAnotherReg(I.getType());
// FIXME: this is probably only right for 32 bit operands.
if (I.getType ()->isSigned()) {
unsigned Tmp = makeAnotherReg (I.getType ());
// Sign extend into the Y register
BuildMI (BB, V8::SRAri, 2, Tmp).addReg (Op0Reg).addZImm (31);
BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (Tmp).addReg (V8::G0);
BuildMI (BB, V8::SDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
} else {
// Zero extend into the Y register, ie, just set it to zero
BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
BuildMI (BB, V8::UDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
}
case Instruction::Div: {
unsigned Opcode = I.getType ()->isSigned () ? V8::SDIVrr : V8::UDIVrr;
// Clear out the Y register (top half of LHS of divide)
BuildMI (BB, V8::WRYrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
BuildMI (BB, V8::NOP, 0); // WR may take up to 4 cycles to finish
BuildMI (BB, V8::NOP, 0);
BuildMI (BB, V8::NOP, 0);
BuildMI (BB, Opcode, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
break;
if (I.getOpcode() == Instruction::Rem) {
unsigned Tmp = makeAnotherReg (I.getType ());
BuildMI (BB, V8::SMULrr, 2, Tmp).addReg(Dest).addReg(Op1Reg);
BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg(Op0Reg).addReg(Tmp);
}
default:
visitInstruction (I);
return;
break;
}
default:
visitInstruction (I);
return;
}
if (OpCase != ~0U) {
static const unsigned Opcodes[] = {
V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr
};
BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
}
switch (getClass (I.getType ())) {

66
lib/Target/SparcV8/InstSelectSimple.cpp
View File

@ -288,33 +288,53 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) {
unsigned Op1Reg = getReg (I.getOperand (1));
unsigned ResultReg = makeAnotherReg (I.getType ());
unsigned OpCase = ~0;
// FIXME: support long, ulong, fp.
switch (I.getOpcode ()) {
case Instruction::Add:
BuildMI (BB, V8::ADDrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
break;
case Instruction::Sub:
BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
break;
case Instruction::Mul: {
unsigned Opcode = I.getType ()->isSigned () ? V8::SMULrr : V8::UMULrr;
BuildMI (BB, Opcode, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
break;
case Instruction::Add: OpCase = 0; break;
case Instruction::Sub: OpCase = 1; break;
case Instruction::Mul: OpCase = 2; break;
case Instruction::And: OpCase = 3; break;
case Instruction::Or: OpCase = 4; break;
case Instruction::Xor: OpCase = 5; break;
case Instruction::Div:
case Instruction::Rem: {
unsigned Dest = ResultReg;
if (I.getOpcode() == Instruction::Rem)
Dest = makeAnotherReg(I.getType());
// FIXME: this is probably only right for 32 bit operands.
if (I.getType ()->isSigned()) {
unsigned Tmp = makeAnotherReg (I.getType ());
// Sign extend into the Y register
BuildMI (BB, V8::SRAri, 2, Tmp).addReg (Op0Reg).addZImm (31);
BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (Tmp).addReg (V8::G0);
BuildMI (BB, V8::SDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
} else {
// Zero extend into the Y register, ie, just set it to zero
BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
BuildMI (BB, V8::UDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
}
case Instruction::Div: {
unsigned Opcode = I.getType ()->isSigned () ? V8::SDIVrr : V8::UDIVrr;
// Clear out the Y register (top half of LHS of divide)
BuildMI (BB, V8::WRYrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
BuildMI (BB, V8::NOP, 0); // WR may take up to 4 cycles to finish
BuildMI (BB, V8::NOP, 0);
BuildMI (BB, V8::NOP, 0);
BuildMI (BB, Opcode, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
break;
if (I.getOpcode() == Instruction::Rem) {
unsigned Tmp = makeAnotherReg (I.getType ());
BuildMI (BB, V8::SMULrr, 2, Tmp).addReg(Dest).addReg(Op1Reg);
BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg(Op0Reg).addReg(Tmp);
}
default:
visitInstruction (I);
return;
break;
}
default:
visitInstruction (I);
return;
}
if (OpCase != ~0U) {
static const unsigned Opcodes[] = {
V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr
};
BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
}
switch (getClass (I.getType ())) {

66
lib/Target/SparcV8/SparcV8ISelSimple.cpp
View File

@ -288,33 +288,53 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) {
unsigned Op1Reg = getReg (I.getOperand (1));
unsigned ResultReg = makeAnotherReg (I.getType ());
unsigned OpCase = ~0;
// FIXME: support long, ulong, fp.
switch (I.getOpcode ()) {
case Instruction::Add:
BuildMI (BB, V8::ADDrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
break;
case Instruction::Sub:
BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
break;
case Instruction::Mul: {
unsigned Opcode = I.getType ()->isSigned () ? V8::SMULrr : V8::UMULrr;
BuildMI (BB, Opcode, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
break;
case Instruction::Add: OpCase = 0; break;
case Instruction::Sub: OpCase = 1; break;
case Instruction::Mul: OpCase = 2; break;
case Instruction::And: OpCase = 3; break;
case Instruction::Or: OpCase = 4; break;
case Instruction::Xor: OpCase = 5; break;
case Instruction::Div:
case Instruction::Rem: {
unsigned Dest = ResultReg;
if (I.getOpcode() == Instruction::Rem)
Dest = makeAnotherReg(I.getType());
// FIXME: this is probably only right for 32 bit operands.
if (I.getType ()->isSigned()) {
unsigned Tmp = makeAnotherReg (I.getType ());
// Sign extend into the Y register
BuildMI (BB, V8::SRAri, 2, Tmp).addReg (Op0Reg).addZImm (31);
BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (Tmp).addReg (V8::G0);
BuildMI (BB, V8::SDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
} else {
// Zero extend into the Y register, ie, just set it to zero
BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
BuildMI (BB, V8::UDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
}
case Instruction::Div: {
unsigned Opcode = I.getType ()->isSigned () ? V8::SDIVrr : V8::UDIVrr;
// Clear out the Y register (top half of LHS of divide)
BuildMI (BB, V8::WRYrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
BuildMI (BB, V8::NOP, 0); // WR may take up to 4 cycles to finish
BuildMI (BB, V8::NOP, 0);
BuildMI (BB, V8::NOP, 0);
BuildMI (BB, Opcode, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
break;
if (I.getOpcode() == Instruction::Rem) {
unsigned Tmp = makeAnotherReg (I.getType ());
BuildMI (BB, V8::SMULrr, 2, Tmp).addReg(Dest).addReg(Op1Reg);
BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg(Op0Reg).addReg(Tmp);
}
default:
visitInstruction (I);
return;
break;
}
default:
visitInstruction (I);
return;
}
if (OpCase != ~0U) {
static const unsigned Opcodes[] = {
V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr
};
BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
}
switch (getClass (I.getType ())) {

20
lib/Target/SparcV8/SparcV8InstrInfo.td
View File

@ -75,9 +75,12 @@ let rd = 0, imm = 0 in
def NOP : F2_1<0b100, "nop">;
// Section B.11 - Logical Instructions, p. 106
def ANDrr : F3_1<2, 0b000001, "and">;
def ANDri : F3_2<2, 0b000001, "and">;
def ORrr : F3_1<2, 0b000010, "or">;
def ORri : F3_2<2, 0b000010, "or">;
def XORrr : F3_1<2, 0b000011, "xor">;
def XORri : F3_2<2, 0b000011, "xor">;
// Section B.12 - Shift Instructions, p. 107
def SLLri : F3_1<2, 0b100101, "sll">;
@ -95,8 +98,14 @@ def UMULrr : F3_1<2, 0b001010, "umul">;
def SMULrr : F3_1<2, 0b001011, "smul">;
// Section B.19 - Divide Instructions, p. 115
def UDIVrr: F3_1<2, 0b001110, "udiv">;
def SDIVrr: F3_1<2, 0b001111, "sdiv">;
def UDIVrr : F3_1<2, 0b001110, "udiv">;
def UDIVri : F3_2<2, 0b001110, "udiv">;
def SDIVrr : F3_1<2, 0b001111, "sdiv">;
def SDIVri : F3_2<2, 0b001111, "sdiv">;
def UDIVCCrr : F3_1<2, 0b011110, "udivcc">;
def UDIVCCri : F3_2<2, 0b011110, "udivcc">;
def SDIVCCrr : F3_1<2, 0b011111, "sdivcc">;
def SDIVCCri : F3_2<2, 0b011111, "sdivcc">;
// Section B.20 - SAVE and RESTORE, p. 117
def SAVErr : F3_1<2, 0b111100, "save">; // save r, r, r
@ -118,7 +127,6 @@ def CALL : InstV8 {
def JMPLrr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
def JMPLri : F3_2<2, 0b111000, "jmpl">; // jmpl [rs1+imm], rd
// Section B.29 - Write State Register Instructions, p. 133
let rd = 0 in
def WRYrr : F3_1<2, 0b110000, "wr">; // Special case of WRASR
def WRASRrr : F3_1<2, 0b110000, "wr">; // Special reg = reg ^ reg
// Section B.29 - Write State Register Instructions
def WRrr : F3_1<2, 0b110000, "wr">; // wr rs1, rs2, rd
def WRri : F3_2<2, 0b110000, "wr">; // wr rs1, imm, rd