mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-19 19:29:31 +00:00
Add a bunch more instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12737 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -288,33 +288,53 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) {
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unsigned Op1Reg = getReg (I.getOperand (1));
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unsigned ResultReg = makeAnotherReg (I.getType ());
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unsigned OpCase = ~0;
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// FIXME: support long, ulong, fp.
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switch (I.getOpcode ()) {
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case Instruction::Add:
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BuildMI (BB, V8::ADDrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
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break;
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case Instruction::Sub:
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BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
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break;
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case Instruction::Mul: {
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unsigned Opcode = I.getType ()->isSigned () ? V8::SMULrr : V8::UMULrr;
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BuildMI (BB, Opcode, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
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break;
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case Instruction::Add: OpCase = 0; break;
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case Instruction::Sub: OpCase = 1; break;
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case Instruction::Mul: OpCase = 2; break;
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case Instruction::And: OpCase = 3; break;
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case Instruction::Or: OpCase = 4; break;
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case Instruction::Xor: OpCase = 5; break;
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case Instruction::Div:
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case Instruction::Rem: {
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unsigned Dest = ResultReg;
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if (I.getOpcode() == Instruction::Rem)
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Dest = makeAnotherReg(I.getType());
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// FIXME: this is probably only right for 32 bit operands.
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if (I.getType ()->isSigned()) {
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unsigned Tmp = makeAnotherReg (I.getType ());
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// Sign extend into the Y register
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BuildMI (BB, V8::SRAri, 2, Tmp).addReg (Op0Reg).addZImm (31);
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BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (Tmp).addReg (V8::G0);
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BuildMI (BB, V8::SDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
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} else {
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// Zero extend into the Y register, ie, just set it to zero
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BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
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BuildMI (BB, V8::UDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
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}
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case Instruction::Div: {
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unsigned Opcode = I.getType ()->isSigned () ? V8::SDIVrr : V8::UDIVrr;
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// Clear out the Y register (top half of LHS of divide)
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BuildMI (BB, V8::WRYrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
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BuildMI (BB, V8::NOP, 0); // WR may take up to 4 cycles to finish
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BuildMI (BB, V8::NOP, 0);
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BuildMI (BB, V8::NOP, 0);
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BuildMI (BB, Opcode, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
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break;
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if (I.getOpcode() == Instruction::Rem) {
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unsigned Tmp = makeAnotherReg (I.getType ());
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BuildMI (BB, V8::SMULrr, 2, Tmp).addReg(Dest).addReg(Op1Reg);
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BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg(Op0Reg).addReg(Tmp);
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}
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default:
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visitInstruction (I);
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return;
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break;
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}
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default:
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visitInstruction (I);
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return;
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}
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if (OpCase != ~0U) {
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static const unsigned Opcodes[] = {
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V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr
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};
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BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
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}
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switch (getClass (I.getType ())) {
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@ -75,9 +75,12 @@ let rd = 0, imm = 0 in
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def NOP : F2_1<0b100, "nop">;
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// Section B.11 - Logical Instructions, p. 106
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def ANDrr : F3_1<2, 0b000001, "and">;
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def ANDri : F3_2<2, 0b000001, "and">;
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def ORrr : F3_1<2, 0b000010, "or">;
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def ORri : F3_2<2, 0b000010, "or">;
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def XORrr : F3_1<2, 0b000011, "xor">;
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def XORri : F3_2<2, 0b000011, "xor">;
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// Section B.12 - Shift Instructions, p. 107
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def SLLri : F3_1<2, 0b100101, "sll">;
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@ -95,8 +98,14 @@ def UMULrr : F3_1<2, 0b001010, "umul">;
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def SMULrr : F3_1<2, 0b001011, "smul">;
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// Section B.19 - Divide Instructions, p. 115
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def UDIVrr: F3_1<2, 0b001110, "udiv">;
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def SDIVrr: F3_1<2, 0b001111, "sdiv">;
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def UDIVrr : F3_1<2, 0b001110, "udiv">;
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def UDIVri : F3_2<2, 0b001110, "udiv">;
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def SDIVrr : F3_1<2, 0b001111, "sdiv">;
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def SDIVri : F3_2<2, 0b001111, "sdiv">;
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def UDIVCCrr : F3_1<2, 0b011110, "udivcc">;
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def UDIVCCri : F3_2<2, 0b011110, "udivcc">;
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def SDIVCCrr : F3_1<2, 0b011111, "sdivcc">;
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def SDIVCCri : F3_2<2, 0b011111, "sdivcc">;
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// Section B.20 - SAVE and RESTORE, p. 117
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def SAVErr : F3_1<2, 0b111100, "save">; // save r, r, r
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@ -118,7 +127,6 @@ def CALL : InstV8 {
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def JMPLrr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
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def JMPLri : F3_2<2, 0b111000, "jmpl">; // jmpl [rs1+imm], rd
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// Section B.29 - Write State Register Instructions, p. 133
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let rd = 0 in
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def WRYrr : F3_1<2, 0b110000, "wr">; // Special case of WRASR
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def WRASRrr : F3_1<2, 0b110000, "wr">; // Special reg = reg ^ reg
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// Section B.29 - Write State Register Instructions
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def WRrr : F3_1<2, 0b110000, "wr">; // wr rs1, rs2, rd
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def WRri : F3_2<2, 0b110000, "wr">; // wr rs1, imm, rd
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@ -288,33 +288,53 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) {
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unsigned Op1Reg = getReg (I.getOperand (1));
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unsigned ResultReg = makeAnotherReg (I.getType ());
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unsigned OpCase = ~0;
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// FIXME: support long, ulong, fp.
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switch (I.getOpcode ()) {
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case Instruction::Add:
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BuildMI (BB, V8::ADDrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
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break;
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case Instruction::Sub:
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BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
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break;
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case Instruction::Mul: {
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unsigned Opcode = I.getType ()->isSigned () ? V8::SMULrr : V8::UMULrr;
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BuildMI (BB, Opcode, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
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break;
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case Instruction::Add: OpCase = 0; break;
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case Instruction::Sub: OpCase = 1; break;
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case Instruction::Mul: OpCase = 2; break;
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case Instruction::And: OpCase = 3; break;
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case Instruction::Or: OpCase = 4; break;
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case Instruction::Xor: OpCase = 5; break;
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case Instruction::Div:
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case Instruction::Rem: {
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unsigned Dest = ResultReg;
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if (I.getOpcode() == Instruction::Rem)
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Dest = makeAnotherReg(I.getType());
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// FIXME: this is probably only right for 32 bit operands.
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if (I.getType ()->isSigned()) {
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unsigned Tmp = makeAnotherReg (I.getType ());
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// Sign extend into the Y register
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BuildMI (BB, V8::SRAri, 2, Tmp).addReg (Op0Reg).addZImm (31);
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BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (Tmp).addReg (V8::G0);
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BuildMI (BB, V8::SDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
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} else {
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// Zero extend into the Y register, ie, just set it to zero
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BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
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BuildMI (BB, V8::UDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
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}
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case Instruction::Div: {
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unsigned Opcode = I.getType ()->isSigned () ? V8::SDIVrr : V8::UDIVrr;
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// Clear out the Y register (top half of LHS of divide)
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BuildMI (BB, V8::WRYrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
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BuildMI (BB, V8::NOP, 0); // WR may take up to 4 cycles to finish
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BuildMI (BB, V8::NOP, 0);
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BuildMI (BB, V8::NOP, 0);
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BuildMI (BB, Opcode, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
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break;
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if (I.getOpcode() == Instruction::Rem) {
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unsigned Tmp = makeAnotherReg (I.getType ());
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BuildMI (BB, V8::SMULrr, 2, Tmp).addReg(Dest).addReg(Op1Reg);
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BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg(Op0Reg).addReg(Tmp);
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}
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default:
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visitInstruction (I);
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return;
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break;
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}
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default:
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visitInstruction (I);
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return;
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}
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if (OpCase != ~0U) {
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static const unsigned Opcodes[] = {
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V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr
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};
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BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
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}
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switch (getClass (I.getType ())) {
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@ -288,33 +288,53 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) {
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unsigned Op1Reg = getReg (I.getOperand (1));
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unsigned ResultReg = makeAnotherReg (I.getType ());
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unsigned OpCase = ~0;
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// FIXME: support long, ulong, fp.
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switch (I.getOpcode ()) {
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case Instruction::Add:
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BuildMI (BB, V8::ADDrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
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break;
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case Instruction::Sub:
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BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
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break;
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case Instruction::Mul: {
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unsigned Opcode = I.getType ()->isSigned () ? V8::SMULrr : V8::UMULrr;
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BuildMI (BB, Opcode, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
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break;
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case Instruction::Add: OpCase = 0; break;
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case Instruction::Sub: OpCase = 1; break;
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case Instruction::Mul: OpCase = 2; break;
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case Instruction::And: OpCase = 3; break;
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case Instruction::Or: OpCase = 4; break;
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case Instruction::Xor: OpCase = 5; break;
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case Instruction::Div:
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case Instruction::Rem: {
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unsigned Dest = ResultReg;
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if (I.getOpcode() == Instruction::Rem)
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Dest = makeAnotherReg(I.getType());
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// FIXME: this is probably only right for 32 bit operands.
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if (I.getType ()->isSigned()) {
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unsigned Tmp = makeAnotherReg (I.getType ());
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// Sign extend into the Y register
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BuildMI (BB, V8::SRAri, 2, Tmp).addReg (Op0Reg).addZImm (31);
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BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (Tmp).addReg (V8::G0);
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BuildMI (BB, V8::SDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
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} else {
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// Zero extend into the Y register, ie, just set it to zero
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BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
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BuildMI (BB, V8::UDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
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}
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case Instruction::Div: {
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unsigned Opcode = I.getType ()->isSigned () ? V8::SDIVrr : V8::UDIVrr;
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// Clear out the Y register (top half of LHS of divide)
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BuildMI (BB, V8::WRYrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
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BuildMI (BB, V8::NOP, 0); // WR may take up to 4 cycles to finish
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BuildMI (BB, V8::NOP, 0);
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BuildMI (BB, V8::NOP, 0);
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BuildMI (BB, Opcode, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
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break;
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if (I.getOpcode() == Instruction::Rem) {
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unsigned Tmp = makeAnotherReg (I.getType ());
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BuildMI (BB, V8::SMULrr, 2, Tmp).addReg(Dest).addReg(Op1Reg);
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BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg(Op0Reg).addReg(Tmp);
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}
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default:
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visitInstruction (I);
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return;
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break;
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}
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default:
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visitInstruction (I);
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return;
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}
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if (OpCase != ~0U) {
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static const unsigned Opcodes[] = {
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V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr
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};
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BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
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}
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switch (getClass (I.getType ())) {
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@ -288,33 +288,53 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) {
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unsigned Op1Reg = getReg (I.getOperand (1));
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unsigned ResultReg = makeAnotherReg (I.getType ());
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unsigned OpCase = ~0;
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// FIXME: support long, ulong, fp.
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switch (I.getOpcode ()) {
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case Instruction::Add:
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BuildMI (BB, V8::ADDrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
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break;
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case Instruction::Sub:
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BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
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break;
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case Instruction::Mul: {
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unsigned Opcode = I.getType ()->isSigned () ? V8::SMULrr : V8::UMULrr;
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BuildMI (BB, Opcode, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
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break;
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case Instruction::Add: OpCase = 0; break;
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case Instruction::Sub: OpCase = 1; break;
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case Instruction::Mul: OpCase = 2; break;
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case Instruction::And: OpCase = 3; break;
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case Instruction::Or: OpCase = 4; break;
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case Instruction::Xor: OpCase = 5; break;
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case Instruction::Div:
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case Instruction::Rem: {
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unsigned Dest = ResultReg;
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if (I.getOpcode() == Instruction::Rem)
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Dest = makeAnotherReg(I.getType());
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// FIXME: this is probably only right for 32 bit operands.
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if (I.getType ()->isSigned()) {
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unsigned Tmp = makeAnotherReg (I.getType ());
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// Sign extend into the Y register
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BuildMI (BB, V8::SRAri, 2, Tmp).addReg (Op0Reg).addZImm (31);
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BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (Tmp).addReg (V8::G0);
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BuildMI (BB, V8::SDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
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} else {
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// Zero extend into the Y register, ie, just set it to zero
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BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
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BuildMI (BB, V8::UDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
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}
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case Instruction::Div: {
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unsigned Opcode = I.getType ()->isSigned () ? V8::SDIVrr : V8::UDIVrr;
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// Clear out the Y register (top half of LHS of divide)
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BuildMI (BB, V8::WRYrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
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BuildMI (BB, V8::NOP, 0); // WR may take up to 4 cycles to finish
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BuildMI (BB, V8::NOP, 0);
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BuildMI (BB, V8::NOP, 0);
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BuildMI (BB, Opcode, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
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break;
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if (I.getOpcode() == Instruction::Rem) {
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unsigned Tmp = makeAnotherReg (I.getType ());
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BuildMI (BB, V8::SMULrr, 2, Tmp).addReg(Dest).addReg(Op1Reg);
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BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg(Op0Reg).addReg(Tmp);
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}
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default:
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visitInstruction (I);
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return;
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break;
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}
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default:
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visitInstruction (I);
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return;
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}
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if (OpCase != ~0U) {
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static const unsigned Opcodes[] = {
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V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr
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};
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BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
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}
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switch (getClass (I.getType ())) {
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@ -75,9 +75,12 @@ let rd = 0, imm = 0 in
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def NOP : F2_1<0b100, "nop">;
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// Section B.11 - Logical Instructions, p. 106
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def ANDrr : F3_1<2, 0b000001, "and">;
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def ANDri : F3_2<2, 0b000001, "and">;
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def ORrr : F3_1<2, 0b000010, "or">;
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def ORri : F3_2<2, 0b000010, "or">;
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def XORrr : F3_1<2, 0b000011, "xor">;
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def XORri : F3_2<2, 0b000011, "xor">;
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// Section B.12 - Shift Instructions, p. 107
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def SLLri : F3_1<2, 0b100101, "sll">;
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@ -95,8 +98,14 @@ def UMULrr : F3_1<2, 0b001010, "umul">;
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def SMULrr : F3_1<2, 0b001011, "smul">;
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// Section B.19 - Divide Instructions, p. 115
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def UDIVrr: F3_1<2, 0b001110, "udiv">;
|
||||
def SDIVrr: F3_1<2, 0b001111, "sdiv">;
|
||||
def UDIVrr : F3_1<2, 0b001110, "udiv">;
|
||||
def UDIVri : F3_2<2, 0b001110, "udiv">;
|
||||
def SDIVrr : F3_1<2, 0b001111, "sdiv">;
|
||||
def SDIVri : F3_2<2, 0b001111, "sdiv">;
|
||||
def UDIVCCrr : F3_1<2, 0b011110, "udivcc">;
|
||||
def UDIVCCri : F3_2<2, 0b011110, "udivcc">;
|
||||
def SDIVCCrr : F3_1<2, 0b011111, "sdivcc">;
|
||||
def SDIVCCri : F3_2<2, 0b011111, "sdivcc">;
|
||||
|
||||
// Section B.20 - SAVE and RESTORE, p. 117
|
||||
def SAVErr : F3_1<2, 0b111100, "save">; // save r, r, r
|
||||
@ -118,7 +127,6 @@ def CALL : InstV8 {
|
||||
def JMPLrr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
|
||||
def JMPLri : F3_2<2, 0b111000, "jmpl">; // jmpl [rs1+imm], rd
|
||||
|
||||
// Section B.29 - Write State Register Instructions, p. 133
|
||||
let rd = 0 in
|
||||
def WRYrr : F3_1<2, 0b110000, "wr">; // Special case of WRASR
|
||||
def WRASRrr : F3_1<2, 0b110000, "wr">; // Special reg = reg ^ reg
|
||||
// Section B.29 - Write State Register Instructions
|
||||
def WRrr : F3_1<2, 0b110000, "wr">; // wr rs1, rs2, rd
|
||||
def WRri : F3_2<2, 0b110000, "wr">; // wr rs1, imm, rd
|
||||
|
Loading…
Reference in New Issue
Block a user