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Add support for ISD::TRAP to the XCore backend

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60479 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne 2008-12-03 10:59:16 +00:00
parent 370e5340a5
commit 269bc0042f
3 changed files with 27 additions and 1 deletions
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2
lib/Target/XCore/XCoreISelLowering.cpp
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@ -106,6 +106,8 @@ XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM)
setOperationAction(ISD::ROTL , MVT::i32, Expand); setOperationAction(ISD::ROTL , MVT::i32, Expand);
setOperationAction(ISD::ROTR , MVT::i32, Expand); setOperationAction(ISD::ROTR , MVT::i32, Expand);
setOperationAction(ISD::TRAP, MVT::Other, Legal);
// Expand jump tables for now // Expand jump tables for now
setOperationAction(ISD::BR_JT, MVT::Other, Expand); setOperationAction(ISD::BR_JT, MVT::Other, Expand);
setOperationAction(ISD::JumpTable, MVT::i32, Custom); setOperationAction(ISD::JumpTable, MVT::i32, Custom);

15
lib/Target/XCore/XCoreInstrInfo.td
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@ -762,7 +762,7 @@ def CLZ_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
// One operand short // One operand short
// TODO edu, eeu, waitet, waitef, freer, tstart, msync, mjoin, syncr, clrtp // TODO edu, eeu, waitet, waitef, freer, tstart, msync, mjoin, syncr, clrtp
// bru, setdp, setcp, setv, setev, kcall, ecallt, ecallf // bru, setdp, setcp, setv, setev, kcall
// dgetreg // dgetreg
let isBranch=1, isIndirectBranch=1, isTerminator=1 in let isBranch=1, isIndirectBranch=1, isTerminator=1 in
def BAU_1r : _F1R<(outs), (ins GRRegs:$addr), def BAU_1r : _F1R<(outs), (ins GRRegs:$addr),
@ -774,6 +774,16 @@ def SETSP_1r : _F1R<(outs), (ins GRRegs:$src),
"set sp, $src", "set sp, $src",
[]>; []>;
let isBarrier = 1, hasCtrlDep = 1 in
def ECALLT_1r : _F1R<(outs), (ins GRRegs:$src),
"ecallt $src",
[]>;
let isBarrier = 1, hasCtrlDep = 1 in
def ECALLF_1r : _F1R<(outs), (ins GRRegs:$src),
"ecallf $src",
[]>;
let isCall=1, let isCall=1,
// All calls clobber the the link register and the non-callee-saved registers: // All calls clobber the the link register and the non-callee-saved registers:
Defs = [R0, R1, R2, R3, R11, LR] in { Defs = [R0, R1, R2, R3, R11, LR] in {
@ -852,6 +862,9 @@ def : Pat<(store GRRegs:$val, GRRegs:$addr),
/// cttz /// cttz
def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>; def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>;
/// trap
def : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>;
/// ///
/// branch patterns /// branch patterns
/// ///

11
test/CodeGen/XCore/trap.ll Normal file
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@ -0,0 +1,11 @@
; RUN: llvm-as < %s | llc -march=xcore > %t1.s
; RUN: grep "ecallf" %t1.s | count 1
; RUN: grep "ldc" %t1.s | count 1
define i32 @test() noreturn nounwind {
entry:
tail call void @llvm.trap( )
unreachable
}
declare void @llvm.trap() nounwind