6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-13 04:30:23 +00:00
Code Issues Projects Releases Wiki Activity

Add Target hook to duplicate machine instructions.

Browse Source 
Some instructions refer to unique labels, and so cannot be trivially cloned
with CloneMachineInstr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92873 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2010-01-06 23:47:07 +00:00
parent ce3e769c15
commit 30ac0467ce
6 changed files with 151 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
include/llvm/Target/TargetInstrInfo.h
View File

@ -232,6 +232,12 @@ public:
const MachineInstr *Orig,
const TargetRegisterInfo *TRI) const = 0;
/// duplicate - Create a duplicate of the Orig instruction in MF. This is like
/// MachineFunction::CloneMachineInstr(), but the target may update operands
/// that are required to be unique.
virtual MachineInstr *duplicate(MachineInstr *Orig,
MachineFunction &MF) const = 0;
/// convertToThreeAddress - This method must be implemented by targets that
/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
/// may be able to convert a two-address instruction into one or more true
@ -560,6 +566,8 @@ public:
unsigned DestReg, unsigned SubReg,
const MachineInstr *Orig,
const TargetRegisterInfo *TRI) const;
virtual MachineInstr *duplicate(MachineInstr *Orig,
MachineFunction &MF) const;
virtual bool isIdentical(const MachineInstr *MI,
const MachineInstr *Other,
const MachineRegisterInfo *MRI) const;

2
lib/CodeGen/TailDuplication.cpp
View File

@ -346,7 +346,7 @@ void TailDuplicatePass::DuplicateInstruction(MachineInstr *MI,
MachineBasicBlock *PredBB,
MachineFunction &MF,
DenseMap<unsigned, unsigned> &LocalVRMap) {
MachineInstr *NewMI = MF.CloneMachineInstr(MI);
MachineInstr *NewMI = TII->duplicate(MI, MF);
for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = NewMI->getOperand(i);
if (!MO.isReg())

7
lib/CodeGen/TargetInstrInfoImpl.cpp
View File

@ -150,6 +150,13 @@ void TargetInstrInfoImpl::reMaterialize(MachineBasicBlock &MBB,
MBB.insert(I, MI);
}
MachineInstr *TargetInstrInfoImpl::duplicate(MachineInstr *Orig,
MachineFunction &MF) const {
assert(!Orig->getDesc().isNotDuplicable() &&
"Instruction cannot be duplicated");
return MF.CloneMachineInstr(Orig);
}
bool
TargetInstrInfoImpl::isIdentical(const MachineInstr *MI,
const MachineInstr *Other,

67
lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -938,6 +938,35 @@ ARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
return false;
}
/// Create a copy of a const pool value. Update CPI to the new index and return
/// the label UID.
static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
MachineConstantPool *MCP = MF.getConstantPool();
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
assert(MCPE.isMachineConstantPoolEntry() &&
"Expecting a machine constantpool entry!");
ARMConstantPoolValue *ACPV =
static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
unsigned PCLabelId = AFI->createConstPoolEntryUId();
ARMConstantPoolValue *NewCPV = 0;
if (ACPV->isGlobalValue())
NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId,
ARMCP::CPValue, 4);
else if (ACPV->isExtSymbol())
NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(),
ACPV->getSymbol(), PCLabelId, 4);
else if (ACPV->isBlockAddress())
NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId,
ARMCP::CPBlockAddress, 4);
else
llvm_unreachable("Unexpected ARM constantpool value type!!");
CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
return PCLabelId;
}
void ARMBaseInstrInfo::
reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
@ -960,28 +989,8 @@ reMaterialize(MachineBasicBlock &MBB,
case ARM::tLDRpci_pic:
case ARM::t2LDRpci_pic: {
MachineFunction &MF = *MBB.getParent();
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
MachineConstantPool *MCP = MF.getConstantPool();
unsigned CPI = Orig->getOperand(1).getIndex();
const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
assert(MCPE.isMachineConstantPoolEntry() &&
"Expecting a machine constantpool entry!");
ARMConstantPoolValue *ACPV =
static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
unsigned PCLabelId = AFI->createConstPoolEntryUId();
ARMConstantPoolValue *NewCPV = 0;
if (ACPV->isGlobalValue())
NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId,
ARMCP::CPValue, 4);
else if (ACPV->isExtSymbol())
NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(),
ACPV->getSymbol(), PCLabelId, 4);
else if (ACPV->isBlockAddress())
NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId,
ARMCP::CPBlockAddress, 4);
else
llvm_unreachable("Unexpected ARM constantpool value type!!");
CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
unsigned PCLabelId = duplicateCPV(MF, CPI);
MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
DestReg)
.addConstantPoolIndex(CPI).addImm(PCLabelId);
@ -994,6 +1003,22 @@ reMaterialize(MachineBasicBlock &MBB,
NewMI->getOperand(0).setSubReg(SubIdx);
}
MachineInstr *
ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF);
switch(Orig->getOpcode()) {
case ARM::tLDRpci_pic:
case ARM::t2LDRpci_pic: {
unsigned CPI = Orig->getOperand(1).getIndex();
unsigned PCLabelId = duplicateCPV(MF, CPI);
Orig->getOperand(1).setIndex(CPI);
Orig->getOperand(2).setImm(PCLabelId);
break;
}
}
return MI;
}
bool ARMBaseInstrInfo::isIdentical(const MachineInstr *MI0,
const MachineInstr *MI1,
const MachineRegisterInfo *MRI) const {

2
lib/Target/ARM/ARMBaseInstrInfo.h
View File

@ -287,6 +287,8 @@ public:
const MachineInstr *Orig,
const TargetRegisterInfo *TRI) const;
MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const;
virtual bool isIdentical(const MachineInstr *MI, const MachineInstr *Other,
const MachineRegisterInfo *MRI) const;
};

87
test/CodeGen/Thumb2/2010-01-06-TailDuplicateLabels.ll Normal file
View File

@ -0,0 +1,87 @@
; RUN: llc -relocation-model=pic -pre-regalloc-taildup < %s | grep {:$} | sort | uniq -d | count 0
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32"
target triple = "thumbv7-apple-darwin10"
%struct.PlatformMutex = type { i32, [40 x i8] }
%struct.SpinLock = type { %struct.PlatformMutex }
%"struct.WTF::TCMalloc_ThreadCache" = type { i32, %struct._opaque_pthread_t*, i8, [68 x %"struct.WTF::TCMalloc_ThreadCache_FreeList"], i32, i32, %"struct.WTF::TCMalloc_ThreadCache"*, %"struct.WTF::TCMalloc_ThreadCache"* }
%"struct.WTF::TCMalloc_ThreadCache_FreeList" = type { i8*, i16, i16 }
%struct.__darwin_pthread_handler_rec = type { void (i8*)*, i8*, %struct.__darwin_pthread_handler_rec* }
%struct._opaque_pthread_t = type { i32, %struct.__darwin_pthread_handler_rec*, [596 x i8] }
@_ZN3WTFL8heap_keyE = internal global i32 0 ; <i32*> [#uses=1]
@_ZN3WTFL10tsd_initedE.b = internal global i1 false ; <i1*> [#uses=2]
@_ZN3WTFL13pageheap_lockE = internal global %struct.SpinLock { %struct.PlatformMutex { i32 850045863, [40 x i8] zeroinitializer } } ; <%struct.SpinLock*> [#uses=1]
@_ZN3WTFL12thread_heapsE = internal global %"struct.WTF::TCMalloc_ThreadCache"* null ; <%"struct.WTF::TCMalloc_ThreadCache"**> [#uses=1]
@llvm.used = appending global [1 x i8*] [i8* bitcast (%"struct.WTF::TCMalloc_ThreadCache"* ()* @_ZN3WTF20TCMalloc_ThreadCache22CreateCacheIfNecessaryEv to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
define arm_apcscc %"struct.WTF::TCMalloc_ThreadCache"* @_ZN3WTF20TCMalloc_ThreadCache22CreateCacheIfNecessaryEv() nounwind {
entry:
%0 = tail call arm_apcscc i32 @pthread_mutex_lock(%struct.PlatformMutex* getelementptr inbounds (%struct.SpinLock* @_ZN3WTFL13pageheap_lockE, i32 0, i32 0)) nounwind
%.b24 = load i1* @_ZN3WTFL10tsd_initedE.b, align 4 ; <i1> [#uses=1]
br i1 %.b24, label %bb5, label %bb6
bb5: ; preds = %entry
%1 = tail call arm_apcscc %struct._opaque_pthread_t* @pthread_self() nounwind
br label %bb6
bb6: ; preds = %bb5, %entry
%me.0 = phi %struct._opaque_pthread_t* [ %1, %bb5 ], [ null, %entry ] ; <%struct._opaque_pthread_t*> [#uses=2]
br label %bb11
bb7: ; preds = %bb11
%2 = getelementptr inbounds %"struct.WTF::TCMalloc_ThreadCache"* %h.0, i32 0, i32 1
%3 = load %struct._opaque_pthread_t** %2, align 4
%4 = tail call arm_apcscc i32 @pthread_equal(%struct._opaque_pthread_t* %3, %struct._opaque_pthread_t* %me.0) nounwind
%5 = icmp eq i32 %4, 0
br i1 %5, label %bb10, label %bb14
bb10: ; preds = %bb7
%6 = getelementptr inbounds %"struct.WTF::TCMalloc_ThreadCache"* %h.0, i32 0, i32 6
br label %bb11
bb11: ; preds = %bb10, %bb6
%h.0.in = phi %"struct.WTF::TCMalloc_ThreadCache"** [ @_ZN3WTFL12thread_heapsE, %bb6 ], [ %6, %bb10 ] ; <%"struct.WTF::TCMalloc_ThreadCache"**> [#uses=1]
%h.0 = load %"struct.WTF::TCMalloc_ThreadCache"** %h.0.in, align 4 ; <%"struct.WTF::TCMalloc_ThreadCache"*> [#uses=4]
%7 = icmp eq %"struct.WTF::TCMalloc_ThreadCache"* %h.0, null
br i1 %7, label %bb13, label %bb7
bb13: ; preds = %bb11
%8 = tail call arm_apcscc %"struct.WTF::TCMalloc_ThreadCache"* @_ZN3WTF20TCMalloc_ThreadCache7NewHeapEP17_opaque_pthread_t(%struct._opaque_pthread_t* %me.0) nounwind
br label %bb14
bb14: ; preds = %bb13, %bb7
%heap.1 = phi %"struct.WTF::TCMalloc_ThreadCache"* [ %8, %bb13 ], [ %h.0, %bb7 ] ; <%"struct.WTF::TCMalloc_ThreadCache"*> [#uses=4]
%9 = tail call arm_apcscc i32 @pthread_mutex_unlock(%struct.PlatformMutex* getelementptr inbounds (%struct.SpinLock* @_ZN3WTFL13pageheap_lockE, i32 0, i32 0)) nounwind
%10 = getelementptr inbounds %"struct.WTF::TCMalloc_ThreadCache"* %heap.1, i32 0, i32 2
%11 = load i8* %10, align 4
%toBool15not = icmp eq i8 %11, 0 ; <i1> [#uses=1]
br i1 %toBool15not, label %bb19, label %bb22
bb19: ; preds = %bb14
%.b = load i1* @_ZN3WTFL10tsd_initedE.b, align 4 ; <i1> [#uses=1]
br i1 %.b, label %bb21, label %bb22
bb21: ; preds = %bb19
store i8 1, i8* %10, align 4
%12 = load i32* @_ZN3WTFL8heap_keyE, align 4
%13 = bitcast %"struct.WTF::TCMalloc_ThreadCache"* %heap.1 to i8*
%14 = tail call arm_apcscc i32 @pthread_setspecific(i32 %12, i8* %13) nounwind
ret %"struct.WTF::TCMalloc_ThreadCache"* %heap.1
bb22: ; preds = %bb19, %bb14
ret %"struct.WTF::TCMalloc_ThreadCache"* %heap.1
}
declare arm_apcscc i32 @pthread_mutex_lock(%struct.PlatformMutex*)
declare arm_apcscc i32 @pthread_mutex_unlock(%struct.PlatformMutex*)
declare hidden arm_apcscc %"struct.WTF::TCMalloc_ThreadCache"* @_ZN3WTF20TCMalloc_ThreadCache7NewHeapEP17_opaque_pthread_t(%struct._opaque_pthread_t*) nounwind
declare arm_apcscc i32 @pthread_setspecific(i32, i8*)
declare arm_apcscc %struct._opaque_pthread_t* @pthread_self()
declare arm_apcscc i32 @pthread_equal(%struct._opaque_pthread_t*, %struct._opaque_pthread_t*)