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Clean up the handling of two-address operands in RegScavenger.

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This fixes PR4528.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78107 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2009-08-04 21:30:30 +00:00
parent f955cbf56f
commit 323e7d32ab
2 changed files with 36 additions and 12 deletions
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15
lib/CodeGen/RegisterScavenging.cpp
View File

@ -224,11 +224,13 @@ void RegScavenger::forward() {
BitVector KillRegs(NumPhysRegs);
for (unsigned i = 0, e = UseMOs.size(); i != e; ++i) {
const MachineOperand MO = *UseMOs[i].first;
unsigned Idx = UseMOs[i].second;
unsigned Reg = MO.getReg();
assert(isUsed(Reg) && "Using an undefined register!");
if (MO.isKill() && !isReserved(Reg)) {
// Two-address operands implicitly kill.
if ((MO.isKill() || MI->isRegTiedToDefOperand(Idx)) && !isReserved(Reg)) {
KillRegs.set(Reg);
// Mark sub-registers as used.
@ -251,8 +253,6 @@ void RegScavenger::forward() {
for (unsigned i = 0, e = NumECs + NumDefs; i != e; ++i) {
const MachineOperand &MO = (i < NumECs)
? *EarlyClobberMOs[i].first : *DefMOs[i-NumECs].first;
unsigned Idx = (i < NumECs)
? EarlyClobberMOs[i].second : DefMOs[i-NumECs].second;
unsigned Reg = MO.getReg();
if (MO.isUndef())
continue;
@ -263,15 +263,6 @@ void RegScavenger::forward() {
continue;
}
// Skip two-address destination operand.
unsigned UseIdx;
if (MI->isRegTiedToUseOperand(Idx, &UseIdx) &&
!MI->getOperand(UseIdx).isUndef()) {
assert(!MI->getOperand(UseIdx).isKill() &&
"Using an undefined register!");
continue;
}
// Skip if this is merely redefining part of a super-register.
if (RedefinesSuperRegPart(MI, MO, TRI))
continue;

33
test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll Normal file
View File

@ -0,0 +1,33 @@
; RUN: llvm-as < %s | llc -mtriple=armv6-elf
; PR4528
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
target triple = "armv6-elf"
define arm_aapcscc i32 @file_read_actor(i32* nocapture %desc, i32* %page, i32 %offset, i32 %size) nounwind optsize {
entry:
br i1 undef, label %fault_in_pages_writeable.exit, label %bb5.i
bb5.i: ; preds = %entry
%asmtmp.i = tail call i32 asm sideeffect "1:\09strbt\09$1,[$2]\0A2:\0A\09.section .fixup,\22ax\22\0A\09.align\092\0A3:\09mov\09$0, $3\0A\09b\092b\0A\09.previous\0A\09.section __ex_table,\22a\22\0A\09.align\093\0A\09.long\091b, 3b\0A\09.previous", "=r,r,r,i,0,~{cc}"(i8 0, i32 undef, i32 -14, i32 0) nounwind ; <i32> [#uses=1]
%0 = icmp eq i32 %asmtmp.i, 0 ; <i1> [#uses=1]
br i1 %0, label %bb6.i, label %fault_in_pages_writeable.exit
bb6.i: ; preds = %bb5.i
br i1 undef, label %fault_in_pages_writeable.exit, label %bb7.i
bb7.i: ; preds = %bb6.i
unreachable
fault_in_pages_writeable.exit: ; preds = %bb6.i, %bb5.i, %entry
br i1 undef, label %bb2, label %bb3
bb2: ; preds = %fault_in_pages_writeable.exit
unreachable
bb3: ; preds = %fault_in_pages_writeable.exit
%1 = tail call arm_aapcscc i32 @__copy_to_user(i8* undef, i8* undef, i32 undef) nounwind ; <i32> [#uses=0]
unreachable
}
declare arm_aapcscc i32 @__copy_to_user(i8*, i8*, i32)