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Add more vector NodeTypes: VSDIV, VUDIV, VAND, VOR, and VXOR.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26504 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2006-03-03 07:01:07 +00:00
parent 33143dce15
commit 3e1ce5a44d
3 changed files with 22 additions and 9 deletions
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3
include/llvm/CodeGen/SelectionDAGNodes.h
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@ -147,7 +147,8 @@ namespace ISD {
// the elements. The order is count, type, op0, op1. All vector opcodes,
// including VLOAD and VConstant must currently have count and type as
// their 1st and 2nd arguments.
VADD, VSUB, VMUL,
VADD, VSUB, VMUL, VSDIV, VUDIV,
VAND, VOR, VXOR,
// MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing
// an unsigned/signed value of type i[2*n], then return the top part.

18
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -152,9 +152,14 @@ private:
static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
switch (VecOp) {
default: assert(0 && "Don't know how to scalarize this opcode!");
case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
case ISD::VSDIV: return MVT::isInteger(VT) ? ISD::SDIV: ISD::FDIV;
case ISD::VUDIV: return MVT::isInteger(VT) ? ISD::UDIV: ISD::FDIV;
case ISD::VAND: return MVT::isInteger(VT) ? ISD::AND : 0;
case ISD::VOR: return MVT::isInteger(VT) ? ISD::OR : 0;
case ISD::VXOR: return MVT::isInteger(VT) ? ISD::XOR : 0;
}
}
@ -3646,7 +3651,12 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
}
case ISD::VADD:
case ISD::VSUB:
case ISD::VMUL: {
case ISD::VMUL:
case ISD::VSDIV:
case ISD::VUDIV:
case ISD::VAND:
case ISD::VOR:
case ISD::VXOR: {
unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(0))->getValue();
MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
MVT::ValueType TVT = (NumElements/2 > 1)

10
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
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@ -496,15 +496,17 @@ public:
}
void visitDiv(User &I) {
const Type *Ty = I.getType();
visitBinary(I, Ty->isSigned() ? ISD::SDIV : ISD::UDIV, ISD::FDIV, 0);
visitBinary(I,
Ty->isSigned() ? ISD::SDIV : ISD::UDIV, ISD::FDIV,
Ty->isSigned() ? ISD::VSDIV : ISD::VUDIV);
}
void visitRem(User &I) {
const Type *Ty = I.getType();
visitBinary(I, Ty->isSigned() ? ISD::SREM : ISD::UREM, ISD::FREM, 0);
}
void visitAnd(User &I) { visitBinary(I, ISD::AND, 0, 0); }
void visitOr (User &I) { visitBinary(I, ISD::OR, 0, 0); }
void visitXor(User &I) { visitBinary(I, ISD::XOR, 0, 0); }
void visitAnd(User &I) { visitBinary(I, ISD::AND, 0, ISD::VAND); }
void visitOr (User &I) { visitBinary(I, ISD::OR, 0, ISD::VOR); }
void visitXor(User &I) { visitBinary(I, ISD::XOR, 0, ISD::VXOR); }
void visitShl(User &I) { visitShift(I, ISD::SHL); }
void visitShr(User &I) {
visitShift(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA);