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Add rotate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19690 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -875,6 +875,69 @@ let isTwoAddress = 0 in {
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"sar{l} {$src, $dst|$dst, $src}">;
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}
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// Rotate instructions
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// FIXME: provide shorter instructions when imm8 == 1
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def ROL8rCL : I<0xD2, MRM0r, (ops R8 :$dst, R8 :$src),
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"rol{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
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def ROL16rCL : I<0xD3, MRM0r, (ops R16:$dst, R16:$src),
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"rol{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
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def ROL32rCL : I<0xD3, MRM0r, (ops R32:$dst, R32:$src),
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"rol{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
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def ROL8ri : Ii8<0xC0, MRM0r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
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"rol{b} {$src2, $dst|$dst, $src2}">;
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def ROL16ri : Ii8<0xC1, MRM0r, (ops R16:$dst, R16:$src1, i8imm:$src2),
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"rol{w} {$src2, $dst|$dst, $src2}">, OpSize;
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def ROL32ri : Ii8<0xC1, MRM0r, (ops R32:$dst, R32:$src1, i8imm:$src2),
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"rol{l} {$src2, $dst|$dst, $src2}">;
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let isTwoAddress = 0 in {
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def ROL8mCL : I<0xD2, MRM0m, (ops i8mem :$dst),
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"rol{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
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def ROL16mCL : I<0xD3, MRM0m, (ops i16mem:$dst),
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"rol{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
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def ROL32mCL : I<0xD3, MRM0m, (ops i32mem:$dst),
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"rol{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
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def ROL8mi : Ii8<0xC0, MRM0m, (ops i8mem :$dst, i8imm:$src),
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"rol{b} {$src, $dst|$dst, $src}">;
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def ROL16mi : Ii8<0xC1, MRM0m, (ops i16mem:$dst, i8imm:$src),
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"rol{w} {$src, $dst|$dst, $src}">, OpSize;
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def ROL32mi : Ii8<0xC1, MRM0m, (ops i32mem:$dst, i8imm:$src),
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"rol{l} {$src, $dst|$dst, $src}">;
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}
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def ROR8rCL : I<0xD2, MRM1r, (ops R8 :$dst, R8 :$src),
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"ror{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
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def ROR16rCL : I<0xD3, MRM1r, (ops R16:$dst, R16:$src),
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"ror{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
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def ROR32rCL : I<0xD3, MRM1r, (ops R32:$dst, R32:$src),
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"ror{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
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def ROR8ri : Ii8<0xC0, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
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"ror{b} {$src2, $dst|$dst, $src2}">;
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def ROR16ri : Ii8<0xC1, MRM1r, (ops R16:$dst, R16:$src1, i8imm:$src2),
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"ror{w} {$src2, $dst|$dst, $src2}">, OpSize;
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def ROR32ri : Ii8<0xC1, MRM1r, (ops R32:$dst, R32:$src1, i8imm:$src2),
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"ror{l} {$src2, $dst|$dst, $src2}">;
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let isTwoAddress = 0 in {
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def ROR8mCL : I<0xD2, MRM1m, (ops i8mem :$dst),
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"ror{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
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def ROR16mCL : I<0xD3, MRM1m, (ops i16mem:$dst),
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"ror{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
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def ROR32mCL : I<0xD3, MRM1m, (ops i32mem:$dst),
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"ror{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
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def ROR8mi : Ii8<0xC0, MRM1m, (ops i8mem :$dst, i8imm:$src),
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"ror{b} {$src, $dst|$dst, $src}">;
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def ROR16mi : Ii8<0xC1, MRM1m, (ops i16mem:$dst, i8imm:$src),
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"ror{w} {$src, $dst|$dst, $src}">, OpSize;
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def ROR32mi : Ii8<0xC1, MRM1m, (ops i32mem:$dst, i8imm:$src),
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"ror{l} {$src, $dst|$dst, $src}">;
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}
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// Double shift instructions (generalizations of rotate)
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def SHLD32rrCL : I<0xA5, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
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"shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}">,
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Imp<[CL],[]>, TB;
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@ -221,6 +221,18 @@ MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr* MI,
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case X86::SAR8ri: return MakeMIInst(X86::SAR8mi , FrameIndex, MI);
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case X86::SAR16ri: return MakeMIInst(X86::SAR16mi, FrameIndex, MI);
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case X86::SAR32ri: return MakeMIInst(X86::SAR32mi, FrameIndex, MI);
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case X86::ROL8rCL: return MakeMInst( X86::ROL8mCL ,FrameIndex, MI);
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case X86::ROL16rCL: return MakeMInst( X86::ROL16mCL,FrameIndex, MI);
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case X86::ROL32rCL: return MakeMInst( X86::ROL32mCL,FrameIndex, MI);
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case X86::ROL8ri: return MakeMIInst(X86::ROL8mi , FrameIndex, MI);
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case X86::ROL16ri: return MakeMIInst(X86::ROL16mi, FrameIndex, MI);
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case X86::ROL32ri: return MakeMIInst(X86::ROL32mi, FrameIndex, MI);
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case X86::ROR8rCL: return MakeMInst( X86::ROR8mCL ,FrameIndex, MI);
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case X86::ROR16rCL: return MakeMInst( X86::ROR16mCL,FrameIndex, MI);
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case X86::ROR32rCL: return MakeMInst( X86::ROR32mCL,FrameIndex, MI);
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case X86::ROR8ri: return MakeMIInst(X86::ROR8mi , FrameIndex, MI);
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case X86::ROR16ri: return MakeMIInst(X86::ROR16mi, FrameIndex, MI);
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case X86::ROR32ri: return MakeMIInst(X86::ROR32mi, FrameIndex, MI);
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case X86::SHLD32rrCL:return MakeMRInst( X86::SHLD32mrCL,FrameIndex, MI);
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case X86::SHLD32rri8:return MakeMRIInst(X86::SHLD32mri8,FrameIndex, MI);
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case X86::SHRD32rrCL:return MakeMRInst( X86::SHRD32mrCL,FrameIndex, MI);
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