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Don't use additional arguments for dss and friends to satisfy DSS_Form,

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when let can do the same thing. Keep the 64bit variants as codegen-only.
While they have a different register class, the encoding is the same for
32bit and 64bit mode. Having both present would otherwise confuse the
disassembler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214636 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Joerg Sonnenberger 2014-08-02 15:09:41 +00:00
parent e411c38de9
commit 419f3804f0
4 changed files with 87 additions and 63 deletions
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114
lib/Target/PowerPC/PPCInstrAltivec.td
View File

@ -258,48 +258,64 @@ class VX2_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
def HasAltivec : Predicate<"PPCSubTarget->hasAltivec()">; def HasAltivec : Predicate<"PPCSubTarget->hasAltivec()">;
let Predicates = [HasAltivec] in { let Predicates = [HasAltivec] in {
let isCodeGenOnly = 1 in { def DSS : DSS_Form<0, 822, (outs), (ins u5imm:$STRM),
def DSS : DSS_Form<822, (outs), "dss $STRM", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dss imm:$STRM)]>,
(ins u5imm:$ZERO0, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2), Deprecated<DeprecatedDST> {
"dss $STRM", IIC_LdStLoad /*FIXME*/, []>, let A = 0;
Deprecated<DeprecatedDST>; let B = 0;
def DSSALL : DSS_Form<822, (outs), }
(ins u5imm:$ONE, u5imm:$ZERO0,u5imm:$ZERO1,u5imm:$ZERO2),
"dssall", IIC_LdStLoad /*FIXME*/, []>, def DSSALL : DSS_Form<1, 822, (outs), (ins),
Deprecated<DeprecatedDST>; "dssall", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dssall)]>,
def DST : DSS_Form<342, (outs), Deprecated<DeprecatedDST> {
(ins u5imm:$ZERO, u5imm:$STRM, gprc:$rA, gprc:$rB), let STRM = 0;
"dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, let A = 0;
Deprecated<DeprecatedDST>; let B = 0;
def DSTT : DSS_Form<342, (outs), }
(ins u5imm:$ONE, u5imm:$STRM, gprc:$rA, gprc:$rB),
"dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, def DST : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
Deprecated<DeprecatedDST>; "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
def DSTST : DSS_Form<374, (outs), [(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM)]>,
(ins u5imm:$ZERO, u5imm:$STRM, gprc:$rA, gprc:$rB),
"dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>,
Deprecated<DeprecatedDST>;
def DSTSTT : DSS_Form<374, (outs),
(ins u5imm:$ONE, u5imm:$STRM, gprc:$rA, gprc:$rB),
"dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>,
Deprecated<DeprecatedDST>; Deprecated<DeprecatedDST>;
def DST64 : DSS_Form<342, (outs), def DSTT : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
(ins u5imm:$ZERO, u5imm:$STRM, g8rc:$rA, gprc:$rB), "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
"dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, [(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM)]>,
Deprecated<DeprecatedDST>; Deprecated<DeprecatedDST>;
def DSTT64 : DSS_Form<342, (outs),
(ins u5imm:$ONE, u5imm:$STRM, g8rc:$rA, gprc:$rB), def DSTST : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
"dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
[(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM)]>,
Deprecated<DeprecatedDST>; Deprecated<DeprecatedDST>;
def DSTST64 : DSS_Form<374, (outs),
(ins u5imm:$ZERO, u5imm:$STRM, g8rc:$rA, gprc:$rB), def DSTSTT : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
"dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
Deprecated<DeprecatedDST>; [(int_ppc_altivec_dststt i32:$rA, i32:$rB, imm:$STRM)]>,
def DSTSTT64 : DSS_Form<374, (outs),
(ins u5imm:$ONE, u5imm:$STRM, g8rc:$rA, gprc:$rB),
"dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>,
Deprecated<DeprecatedDST>; Deprecated<DeprecatedDST>;
let isCodeGenOnly = 1 in {
// The very same instructions as above, but formally matching 64bit registers.
def DST64 : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
"dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
[(int_ppc_altivec_dst i64:$rA, i32:$rB, imm:$STRM)]>,
Deprecated<DeprecatedDST>;
def DSTT64 : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
"dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
[(int_ppc_altivec_dstt i64:$rA, i32:$rB, imm:$STRM)]>,
Deprecated<DeprecatedDST>;
def DSTST64 : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
"dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
[(int_ppc_altivec_dstst i64:$rA, i32:$rB,
imm:$STRM)]>,
Deprecated<DeprecatedDST>;
def DSTSTT64 : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
"dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
[(int_ppc_altivec_dststt i64:$rA, i32:$rB,
imm:$STRM)]>,
Deprecated<DeprecatedDST>;
} }
def MFVSCR : VXForm_4<1540, (outs vrrc:$vD), (ins), def MFVSCR : VXForm_4<1540, (outs vrrc:$vD), (ins),
@ -747,30 +763,6 @@ def V_SETALLONES : VXForm_3<908, (outs vrrc:$vD), (ins),
// Additional Altivec Patterns // Additional Altivec Patterns
// //
// DS* intrinsics
def : Pat<(int_ppc_altivec_dssall), (DSSALL 1, 0, 0, 0)>;
def : Pat<(int_ppc_altivec_dss imm:$STRM), (DSS 0, imm:$STRM, 0, 0)>;
// * 32-bit
def : Pat<(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM),
(DST 0, imm:$STRM, $rA, $rB)>;
def : Pat<(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM),
(DSTT 1, imm:$STRM, $rA, $rB)>;
def : Pat<(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM),
(DSTST 0, imm:$STRM, $rA, $rB)>;
def : Pat<(int_ppc_altivec_dststt i32:$rA, i32:$rB, imm:$STRM),
(DSTSTT 1, imm:$STRM, $rA, $rB)>;
// * 64-bit
def : Pat<(int_ppc_altivec_dst i64:$rA, i32:$rB, imm:$STRM),
(DST64 0, imm:$STRM, $rA, $rB)>;
def : Pat<(int_ppc_altivec_dstt i64:$rA, i32:$rB, imm:$STRM),
(DSTT64 1, imm:$STRM, $rA, $rB)>;
def : Pat<(int_ppc_altivec_dstst i64:$rA, i32:$rB, imm:$STRM),
(DSTST64 0, imm:$STRM, $rA, $rB)>;
def : Pat<(int_ppc_altivec_dststt i64:$rA, i32:$rB, imm:$STRM),
(DSTSTT64 1, imm:$STRM, $rA, $rB)>;
// Loads. // Loads.
def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>; def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>;

3
lib/Target/PowerPC/PPCInstrFormats.td
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@ -800,10 +800,9 @@ class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr,
// DSS_Form - Form X instruction, used for altivec dss* instructions. // DSS_Form - Form X instruction, used for altivec dss* instructions.
class DSS_Form<bits<10> xo, dag OOL, dag IOL, string asmstr, class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: I<31, OOL, IOL, asmstr, itin> { : I<31, OOL, IOL, asmstr, itin> {
bits<1> T;
bits<2> STRM; bits<2> STRM;
bits<5> A; bits<5> A;
bits<5> B; bits<5> B;

13
test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt
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@ -2255,3 +2255,16 @@
0x4c 0x00 0x00 0x4e 0x4c 0x00 0x00 0x4e
# CHECK: rfmci # CHECK: rfmci
0x4c 0x00 0x00 0x4c 0x4c 0x00 0x00 0x4c
# CHECK: dss 3
0x7c 0x60 0x06 0x6c
# CHECK: dssall
0x7e 0x00 0x06 0x6c
# CHECK: dst 12, 11, 3
0x7c 0x6c 0x5a 0xac
# CHECK: dstt 12, 11, 3
0x7e 0x6c 0x5a 0xac
# CHECK: dstst 12, 11, 3
0x7c 0x6c 0x5a 0xec
# CHECK: dststt 12, 11, 3
0x7e 0x6c 0x5a 0xec

20
test/MC/PowerPC/ppc64-encoding-ext.s
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@ -3593,3 +3593,23 @@
# CHECK-BE: rfmci # encoding: [0x4c,0x00,0x00,0x4c] # CHECK-BE: rfmci # encoding: [0x4c,0x00,0x00,0x4c]
# CHECK-LE: rfmci # encoding: [0x4c,0x00,0x00,0x4c] # CHECK-LE: rfmci # encoding: [0x4c,0x00,0x00,0x4c]
rfmci rfmci
# Altivec Data Stream instruction:
# CHECK-BE: dss 3 # encoding: [0x7c,0x60,0x06,0x6c]
# CHECK-LE: dss 3 # encoding: [0x6c,0x06,0x60,0x7c]
dss 3
# CHECK-BE: dssall # encoding: [0x7e,0x00,0x06,0x6c]
# CHECK-LE: dssall # encoding: [0x6c,0x06,0x00,0x7e]
dssall
# CHECK-BE: dst 12, 11, 3 # encoding: [0x7c,0x6c,0x5a,0xac]
# CHECK-LE: dst 12, 11, 3 # encoding: [0xac,0x5a,0x6c,0x7c]
dst %r12, %r11, 3
# CHECK-BE: dstt 12, 11, 3 # encoding: [0x7e,0x6c,0x5a,0xac]
# CHECK-LE: dstt 12, 11, 3 # encoding: [0xac,0x5a,0x6c,0x7e]
dstt %r12, %r11, 3
# CHECK-BE: dstst 12, 11, 3 # encoding: [0x7c,0x6c,0x5a,0xec]
# CHECK-LE: dstst 12, 11, 3 # encoding: [0xec,0x5a,0x6c,0x7c]
dstst %r12, %r11, 3
# CHECK-BE: dststt 12, 11, 3 # encoding: [0x7e,0x6c,0x5a,0xec]
# CHECK-LE: dststt 12, 11, 3 # encoding: [0xec,0x5a,0x6c,0x7e]
dststt %r12, %r11, 3