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Turn expanded shift operations into (e.g.) SHL_PARTS if the target supports it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21002 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -125,8 +125,8 @@ private:
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SDOperand Source);
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bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
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SDOperand &Lo, SDOperand &Hi);
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void ExpandAddSub(bool isAdd, SDOperand Op, SDOperand Amt,
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SDOperand &Lo, SDOperand &Hi);
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void ExpandByParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
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SDOperand &Lo, SDOperand &Hi);
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SDOperand getIntPtrConstant(uint64_t Val) {
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return DAG.getConstant(Val, TLI.getPointerTy());
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@ -1288,8 +1288,9 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
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/// ExpandAddSub - Find a clever way to expand this add operation into
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/// subcomponents.
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void SelectionDAGLegalize::ExpandAddSub(bool isAdd, SDOperand LHS,SDOperand RHS,
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SDOperand &Lo, SDOperand &Hi) {
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void SelectionDAGLegalize::
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ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS,
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SDOperand &Lo, SDOperand &Hi) {
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// Expand the subcomponents.
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SDOperand LHSL, LHSH, RHSL, RHSH;
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ExpandOp(LHS, LHSL, LHSH);
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@ -1297,13 +1298,12 @@ void SelectionDAGLegalize::ExpandAddSub(bool isAdd, SDOperand LHS,SDOperand RHS,
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// Convert this add to the appropriate ADDC pair. The low part has no carry
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// in.
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unsigned Opc = isAdd ? ISD::ADD_PARTS : ISD::SUB_PARTS;
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std::vector<SDOperand> Ops;
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Ops.push_back(LHSL);
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Ops.push_back(LHSH);
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Ops.push_back(RHSL);
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Ops.push_back(RHSH);
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Lo = DAG.getNode(Opc, LHSL.getValueType(), Ops);
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Lo = DAG.getNode(NodeOp, LHSL.getValueType(), Ops);
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Hi = Lo.getValue(1);
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}
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@ -1313,6 +1313,10 @@ void SelectionDAGLegalize::ExpandAddSub(bool isAdd, SDOperand LHS,SDOperand RHS,
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/// low-parts expanded into Lo and Hi.
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bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
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SDOperand &Lo, SDOperand &Hi) {
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// FIXME: This code is buggy, disable it for now. Note that we should at
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// least handle the case when Amt is an immediate here.
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return false;
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assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
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"This is not a shift!");
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MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
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@ -1746,6 +1750,14 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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// If we can emit an efficient shift operation, do so now.
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if (ExpandShift(ISD::SHL, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
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break;
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// If this target supports SHL_PARTS, use it.
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if (TLI.getOperationAction(ISD::SHL_PARTS, NVT) == TargetLowering::Legal) {
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ExpandByParts(ISD::SHL_PARTS, Node->getOperand(0), Node->getOperand(1),
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Lo, Hi);
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break;
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}
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// Otherwise, emit a libcall.
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Lo = ExpandLibCall("__ashldi3", Node, Hi);
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break;
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@ -1754,6 +1766,14 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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// If we can emit an efficient shift operation, do so now.
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if (ExpandShift(ISD::SRA, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
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break;
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// If this target supports SRA_PARTS, use it.
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if (TLI.getOperationAction(ISD::SRA_PARTS, NVT) == TargetLowering::Legal) {
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ExpandByParts(ISD::SRA_PARTS, Node->getOperand(0), Node->getOperand(1),
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Lo, Hi);
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break;
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}
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// Otherwise, emit a libcall.
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Lo = ExpandLibCall("__ashrdi3", Node, Hi);
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break;
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@ -1761,15 +1781,25 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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// If we can emit an efficient shift operation, do so now.
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if (ExpandShift(ISD::SRL, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
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break;
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// If this target supports SRL_PARTS, use it.
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if (TLI.getOperationAction(ISD::SRL_PARTS, NVT) == TargetLowering::Legal) {
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ExpandByParts(ISD::SRL_PARTS, Node->getOperand(0), Node->getOperand(1),
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Lo, Hi);
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break;
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}
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// Otherwise, emit a libcall.
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Lo = ExpandLibCall("__lshrdi3", Node, Hi);
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break;
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case ISD::ADD:
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ExpandAddSub(true, Node->getOperand(0), Node->getOperand(1), Lo, Hi);
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case ISD::ADD:
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ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1),
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Lo, Hi);
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break;
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case ISD::SUB:
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ExpandAddSub(false, Node->getOperand(0), Node->getOperand(1), Lo, Hi);
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ExpandByParts(ISD::SUB_PARTS, Node->getOperand(0), Node->getOperand(1),
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Lo, Hi);
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break;
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case ISD::MUL: Lo = ExpandLibCall("__muldi3" , Node, Hi); break;
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case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break;
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