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Verify the order of tied operands in inline asm.

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When there are multiple tied use-def pairs on an inline asm instruction,
the tied uses must appear in the same order as the defs.

It is possible to write an LLVM IR inline asm instruction that breaks
this constraint, but there is no reason for a front end to emit the
operands out of order.

The gnu inline asm syntax specifies tied operands as a single read/write
constraint "+r", so ouf of order operands are not possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162878 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2012-08-29 23:52:52 +00:00
parent 4d69a8c8b2
commit 492d76b02e
1 changed files with 12 additions and 0 deletions
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12
lib/CodeGen/SelectionDAG/InstrEmitter.cpp
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@ -895,6 +895,7 @@ EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
// Remember to operand index of the group flags.
SmallVector<unsigned, 8> GroupIdx;
unsigned PrevDefGroup = 0;
// Add all of the operand registers to the instruction.
for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
@ -943,9 +944,20 @@ EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) {
unsigned DefGroup = 0;
if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) {
// Check that the def groups are monotonically increasing.
// Otherwise, the tied uses and defs won't line up, and
// MI::findTiedOperandIdx() will find the wrong operand. This
// should be automatically enforced by the front ends when
// translating "+" constraints into tied def+use pairs.
assert(DefGroup >= PrevDefGroup &&
"Tied inline asm operands must be in increasing order.");
PrevDefGroup = DefGroup;
unsigned DefIdx = GroupIdx[DefGroup] + 1;
unsigned UseIdx = GroupIdx.back() + 1;
for (unsigned j = 0; j != NumVals; ++j) {
assert(!MI->getOperand(DefIdx + j).isTied() &&
"Def is already tied to another use");
MI->getOperand(DefIdx + j).setIsTied();
MI->getOperand(UseIdx + j).setIsTied();
}