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Do materialize for floating point

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Summary:
start to do simple constants

finish simplestore

add test case

format

Merge branch 'master' into 1756_8

Add basic functionality for assignment of ints. This creates a lot of core infrastructure in which to add, with little effort, quite a bit more to mips fast-isel

Merge branch 'master' into 1756_8

Add basic functionality for assignment of ints. This creates a lot of core infrastructure in which to add, with little effort, quite a bit more to mips fast-isel

in progress

finish integer materialize

test cases

test cases

in progress

Finish up fast-isel materialize for ints.

Finish materialize for ints

test cases

simplestorei.ll

Merge branch 'master' into 1756_8

fix fp constants for fast-isel

Merge branch '1758_1' of dmz-portal.mips.com:llvm into 1758_1

in progress

lastest for fp materialization

clean up

Merge branch 'master' into 1758_1

formatting

add test case

finish test case

Merge branch 'master' into 1758_2

Test Plan:
simplestore.ll

simplestore.ll

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3659

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210414 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Reed Kotler
2014-06-08 03:30:32 +00:00
parent cf7742cb63
commit 4a0c1d135e
2 changed files with 62 additions and 2 deletions
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25
lib/Target/Mips/MipsFastISel.cpp
View File

@@ -167,9 +167,14 @@ bool MipsFastISel::EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
//
// more cases will be handled here in following patches.
//
if (VT != MVT::i32)
if (VT == MVT::i32)
EmitInstStore(Mips::SW, SrcReg, Addr.Base.Reg, Addr.Offset);
else if (VT == MVT::f32)
EmitInstStore(Mips::SWC1, SrcReg, Addr.Base.Reg, Addr.Offset);
else if (VT == MVT::f64)
EmitInstStore(Mips::SDC1, SrcReg, Addr.Base.Reg, Addr.Offset);
else
return false;
EmitInstStore(Mips::SW, SrcReg, Addr.Base.Reg, Addr.Offset);
return true;
}
@@ -229,6 +234,22 @@ bool MipsFastISel::TargetSelectInstruction(const Instruction *I) {
}
unsigned MipsFastISel::MaterializeFP(const ConstantFP *CFP, MVT VT) {
int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
if (VT == MVT::f32) {
const TargetRegisterClass *RC = &Mips::FGR32RegClass;
unsigned DestReg = createResultReg(RC);
unsigned TempReg = Materialize32BitInt(Imm, &Mips::GPR32RegClass);
EmitInst(Mips::MTC1, DestReg).addReg(TempReg);
return DestReg;
} else if (VT == MVT::f64) {
const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
unsigned DestReg = createResultReg(RC);
unsigned TempReg1 = Materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
unsigned TempReg2 =
Materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
EmitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
return DestReg;
}
return 0;
}