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https://github.com/c64scene-ar/llvm-6502.git
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Update gcc 4.3 warnings fix patch with recent head changes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47368 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -13,8 +13,6 @@
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#include "llvm/PassManager.h"
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#include "llvm/ADT/SmallVector.h"
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class llvm::PMDataManager;
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class llvm::PMStack;
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//===----------------------------------------------------------------------===//
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// Overview:
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@ -47,11 +47,12 @@ inline unsigned numVbrBytes(unsigned num) {
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// small ones and four for large ones. We expect this to access file offsets
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// in the 2^10 to 2^24 range and symbol lengths in the 2^0 to 2^8 range,
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// so this approach is reasonable.
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if (num < 1<<14)
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if (num < 1<<14) {
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if (num < 1<<7)
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return 1;
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else
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return 2;
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}
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if (num < 1<<21)
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return 3;
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@ -162,11 +162,12 @@ bool AsmPrinter::doFinalization(Module &M) {
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// If the aliasee has external weak linkage it can be referenced only by
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// alias itself. In this case it can be not in ExtWeakSymbols list. Emit
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// weak reference in such case.
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if (GV->hasExternalWeakLinkage())
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if (GV->hasExternalWeakLinkage()) {
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if (TAI->getWeakRefDirective())
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O << TAI->getWeakRefDirective() << Target << "\n";
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else
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O << "\t.globl\t" << Target << "\n";
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}
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}
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}
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@ -278,9 +278,10 @@ bool IfConverter::runOnMachineFunction(MachineFunction &MF) {
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: BBI.TrueBB->getNumber()) << ") ";
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RetVal = IfConvertSimple(BBI, Kind);
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DOUT << (RetVal ? "succeeded!" : "failed!") << "\n";
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if (RetVal)
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if (RetVal) {
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if (isFalse) NumSimpleFalse++;
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else NumSimple++;
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}
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break;
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}
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case ICTriangle:
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@ -217,7 +217,7 @@ LiveInterval::addRangeFrom(LiveRange LR, iterator From) {
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// Otherwise, if this range ends in the middle of, or right next to, another
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// interval, merge it into that interval.
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if (it != ranges.end())
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if (it != ranges.end()) {
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if (LR.valno == it->valno) {
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if (it->start <= End) {
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it = extendIntervalStartTo(it, Start);
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@ -237,6 +237,7 @@ LiveInterval::addRangeFrom(LiveRange LR, iterator From) {
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assert(it->start >= End &&
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"Cannot overlap two LiveRanges with differing ValID's");
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}
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}
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// Otherwise, this is just a new range that doesn't interact with anything.
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// Insert it.
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@ -695,7 +695,7 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
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// Unallocatable register dead, ignore.
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continue;
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} else {
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assert(!PhysRegsUsed[PhysReg] || PhysRegsUsed[PhysReg] == -1 &&
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assert((!PhysRegsUsed[PhysReg] || PhysRegsUsed[PhysReg] == -1) &&
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"Silently clearing a virtual register?");
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}
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@ -832,11 +832,12 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
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// Spill all physical registers holding virtual registers now.
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for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i)
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if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
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if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) {
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if (unsigned VirtReg = PhysRegsUsed[i])
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spillVirtReg(MBB, MI, VirtReg, i);
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else
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removePhysReg(i);
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}
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}
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/// runOnMachineFunction - Register allocate the whole function
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@ -1996,11 +1996,12 @@ SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
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LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
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if (ConstantSDNode *SUBC =
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dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
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if (SUBC->getValue() == OpSizeInBits)
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if (SUBC->getValue() == OpSizeInBits) {
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if (HasROTL)
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return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
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else
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return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
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}
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}
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}
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@ -2010,11 +2011,12 @@ SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
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RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
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if (ConstantSDNode *SUBC =
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dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
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if (SUBC->getValue() == OpSizeInBits)
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if (SUBC->getValue() == OpSizeInBits) {
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if (HasROTL)
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return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
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else
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return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
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}
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}
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}
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@ -2230,7 +2232,7 @@ SDOperand DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
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// the constant which would cause it to be modified for this
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// operation.
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if (N->getOpcode() == ISD::SRA) {
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uint64_t BinOpRHSSign = BinOpCst->getValue() >> MVT::getSizeInBits(VT)-1;
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uint64_t BinOpRHSSign = BinOpCst->getValue() >> (MVT::getSizeInBits(VT)-1);
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if ((bool)BinOpRHSSign != HighBitSet)
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return SDOperand();
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}
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@ -2552,7 +2554,7 @@ SDOperand DAGCombiner::visitSELECT(SDNode *N) {
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return SDOperand(N, 0); // Don't revisit N.
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// fold selects based on a setcc into other things, such as min/max/abs
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if (N0.getOpcode() == ISD::SETCC)
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if (N0.getOpcode() == ISD::SETCC) {
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// FIXME:
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// Check against MVT::Other for SELECT_CC, which is a workaround for targets
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// having to say they don't support SELECT_CC on every type the DAG knows
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@ -2562,6 +2564,7 @@ SDOperand DAGCombiner::visitSELECT(SDNode *N) {
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N1, N2, N0.getOperand(2));
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else
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return SimplifySelect(N0, N1, N2);
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}
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return SDOperand();
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}
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@ -4013,8 +4016,8 @@ bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
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if (!((Use->getOpcode() == ISD::LOAD &&
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cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
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(Use->getOpcode() == ISD::STORE) &&
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cast<StoreSDNode>(Use)->getBasePtr() == Ptr))
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(Use->getOpcode() == ISD::STORE &&
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cast<StoreSDNode>(Use)->getBasePtr() == Ptr)))
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RealUse = true;
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}
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if (!RealUse)
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@ -4131,8 +4134,8 @@ bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
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SDNode *UseUse = *III;
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if (!((UseUse->getOpcode() == ISD::LOAD &&
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cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) ||
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(UseUse->getOpcode() == ISD::STORE) &&
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cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use))
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(UseUse->getOpcode() == ISD::STORE &&
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cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use)))
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RealUse = true;
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}
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@ -1269,15 +1269,18 @@ bool bu_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
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unsigned RScratch = calcMaxScratches(right);
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if (LScratch > RScratch)
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return true;
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else if (LScratch == RScratch)
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else if (LScratch == RScratch) {
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if (left->Height > right->Height)
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return true;
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else if (left->Height == right->Height)
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else if (left->Height == right->Height) {
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if (left->Depth < right->Depth)
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return true;
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else if (left->Depth == right->Depth)
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else if (left->Depth == right->Depth) {
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if (left->CycleBound > right->CycleBound)
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return true;
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}
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}
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}
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}
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}
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return false;
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@ -1509,15 +1512,19 @@ bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
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if (LPriority+LBonus < RPriority+RBonus)
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return true;
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else if (LPriority == RPriority)
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else if (LPriority == RPriority) {
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if (left->Depth < right->Depth)
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return true;
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else if (left->Depth == right->Depth)
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else if (left->Depth == right->Depth) {
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if (left->NumSuccsLeft > right->NumSuccsLeft)
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return true;
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else if (left->NumSuccsLeft == right->NumSuccsLeft)
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else if (left->NumSuccsLeft == right->NumSuccsLeft) {
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if (left->CycleBound > right->CycleBound)
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return true;
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}
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}
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}
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return false;
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}
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}
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}
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}
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if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val))
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if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) {
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if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.Val)) {
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// No compile time operations on this type yet.
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if (N1C->getValueType(0) == MVT::ppcf128)
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@ -1127,7 +1127,8 @@ SDOperand SelectionDAG::FoldSetCC(MVT::ValueType VT, SDOperand N1,
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// Ensure that the constant occurs on the RHS.
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return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond));
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}
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}
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// Could not fold it.
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return SDOperand();
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}
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@ -2334,20 +2335,22 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
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break;
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}
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case ISD::SELECT:
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if (N1C)
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if (N1C->getValue())
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if (N1C) {
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if (N1C->getValue())
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return N2; // select true, X, Y -> X
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else
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return N3; // select false, X, Y -> Y
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}
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if (N2 == N3) return N2; // select C, X, X -> X
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break;
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case ISD::BRCOND:
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if (N2C)
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if (N2C) {
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if (N2C->getValue()) // Unconditional branch
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return getNode(ISD::BR, MVT::Other, N1, N3);
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else
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return N1; // Never-taken branch
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}
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break;
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case ISD::VECTOR_SHUFFLE:
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assert(VT == N1.getValueType() && VT == N2.getValueType() &&
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@ -2602,7 +2602,7 @@ void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
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static GlobalVariable *ExtractTypeInfo (Value *V) {
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V = IntrinsicInst::StripPointerCasts(V);
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GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
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assert (GV || isa<ConstantPointerNull>(V) &&
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assert ((GV || isa<ConstantPointerNull>(V)) &&
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"TypeInfo must be a global variable or NULL");
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return GV;
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}
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MachineInstr &MI = *MII;
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for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI.getOperand(i);
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if (MO.isRegister() && MO.getReg())
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if (MO.isRegister() && MO.getReg()) {
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if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
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unsigned VirtReg = MO.getReg();
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unsigned PhysReg = VRM.getPhys(VirtReg);
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@ -220,6 +220,7 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
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} else {
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MF.getRegInfo().setPhysRegUsed(MO.getReg());
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}
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}
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}
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DOUT << '\t' << MI;
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@ -385,16 +385,16 @@ static GenericValue executeFCMP_OGT(GenericValue Src1, GenericValue Src2,
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return Dest;
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}
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#define IMPLEMENT_UNORDERED(TY, X,Y) \
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if (TY == Type::FloatTy) \
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if (X.FloatVal != X.FloatVal || Y.FloatVal != Y.FloatVal) { \
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Dest.IntVal = APInt(1,true); \
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return Dest; \
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} \
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else if (X.DoubleVal != X.DoubleVal || Y.DoubleVal != Y.DoubleVal) { \
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Dest.IntVal = APInt(1,true); \
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return Dest; \
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}
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#define IMPLEMENT_UNORDERED(TY, X,Y) \
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if (TY == Type::FloatTy) { \
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if (X.FloatVal != X.FloatVal || Y.FloatVal != Y.FloatVal) { \
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Dest.IntVal = APInt(1,true); \
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return Dest; \
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} \
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} else if (X.DoubleVal != X.DoubleVal || Y.DoubleVal != Y.DoubleVal) { \
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Dest.IntVal = APInt(1,true); \
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return Dest; \
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}
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static GenericValue executeFCMP_UEQ(GenericValue Src1, GenericValue Src2,
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@ -901,11 +901,12 @@ void Interpreter::visitCallSite(CallSite CS) {
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// We do this by zero or sign extending the value as appropriate
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// according to the parameter attributes
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const Type *Ty = V->getType();
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if (Ty->isInteger() && (ArgVals.back().IntVal.getBitWidth() < 32))
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if (Ty->isInteger() && (ArgVals.back().IntVal.getBitWidth() < 32)) {
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if (CS.paramHasAttr(pNum, ParamAttr::ZExt))
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ArgVals.back().IntVal = ArgVals.back().IntVal.zext(32);
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else if (CS.paramHasAttr(pNum, ParamAttr::SExt))
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ArgVals.back().IntVal = ArgVals.back().IntVal.sext(32);
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}
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}
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// To handle indirect calls, we must get the pointer value from the argument
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