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Combine FMA4 SS/SD patterns with the instruction definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147365 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -98,22 +98,26 @@ defm VFNMSUB : fma3s_forms<0x9F, 0xAF, 0xBF, "vfnmsub">;
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//===----------------------------------------------------------------------===//
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multiclass fma4s<bits<8> opc, string OpcodeStr, Operand memop> {
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multiclass fma4s<bits<8> opc, string OpcodeStr, Operand memop,
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ComplexPattern mem_cpat, Intrinsic Int> {
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def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, XOP_W;
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[(set VR128:$dst,
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(Int VR128:$src1, VR128:$src2, VR128:$src3))]>, XOP_W;
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def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, memop:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, XOP_W;
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[(set VR128:$dst,
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(Int VR128:$src1, VR128:$src2, mem_cpat:$src3))]>, XOP_W;
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def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, memop:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>;
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[(set VR128:$dst,
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(Int VR128:$src1, mem_cpat:$src2, VR128:$src3))]>;
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}
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multiclass fma4p<bits<8> opc, string OpcodeStr,
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@ -158,26 +162,34 @@ multiclass fma4p<bits<8> opc, string OpcodeStr,
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}
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let isAsmParserOnly = 1 in {
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defm VFMADDSS4 : fma4s<0x6A, "vfmaddss", ssmem>;
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defm VFMADDSD4 : fma4s<0x6B, "vfmaddsd", sdmem>;
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defm VFMADDSS4 : fma4s<0x6A, "vfmaddss", ssmem, sse_load_f32,
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int_x86_fma4_vfmadd_ss>;
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defm VFMADDSD4 : fma4s<0x6B, "vfmaddsd", sdmem, sse_load_f64,
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int_x86_fma4_vfmadd_sd>;
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defm VFMADDPS4 : fma4p<0x68, "vfmaddps", int_x86_fma4_vfmadd_ps,
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int_x86_fma4_vfmadd_ps_256, memopv4f32, memopv8f32>;
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defm VFMADDPD4 : fma4p<0x69, "vfmaddpd", int_x86_fma4_vfmadd_pd,
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int_x86_fma4_vfmadd_pd_256, memopv2f64, memopv4f64>;
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defm VFMSUBSS4 : fma4s<0x6E, "vfmsubss", ssmem>;
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defm VFMSUBSD4 : fma4s<0x6F, "vfmsubsd", sdmem>;
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defm VFMSUBSS4 : fma4s<0x6E, "vfmsubss", ssmem, sse_load_f32,
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int_x86_fma4_vfmsub_ss>;
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defm VFMSUBSD4 : fma4s<0x6F, "vfmsubsd", sdmem, sse_load_f64,
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int_x86_fma4_vfmsub_sd>;
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defm VFMSUBPS4 : fma4p<0x6C, "vfmsubps", int_x86_fma4_vfmsub_ps,
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int_x86_fma4_vfmsub_ps_256, memopv4f32, memopv8f32>;
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defm VFMSUBPD4 : fma4p<0x6D, "vfmsubpd", int_x86_fma4_vfmsub_pd,
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int_x86_fma4_vfmsub_pd_256, memopv2f64, memopv4f64>;
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defm VFNMADDSS4 : fma4s<0x7A, "vfnmaddss", ssmem>;
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defm VFNMADDSD4 : fma4s<0x7B, "vfnmaddsd", sdmem>;
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defm VFNMADDSS4 : fma4s<0x7A, "vfnmaddss", ssmem, sse_load_f32,
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int_x86_fma4_vfnmadd_ss>;
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defm VFNMADDSD4 : fma4s<0x7B, "vfnmaddsd", sdmem, sse_load_f64,
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int_x86_fma4_vfnmadd_sd>;
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defm VFNMADDPS4 : fma4p<0x78, "vfnmaddps", int_x86_fma4_vfnmadd_ps,
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int_x86_fma4_vfnmadd_ps_256, memopv4f32, memopv8f32>;
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defm VFNMADDPD4 : fma4p<0x79, "vfnmaddpd", int_x86_fma4_vfnmadd_pd,
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int_x86_fma4_vfnmadd_pd_256, memopv2f64, memopv4f64>;
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defm VFNMSUBSS4 : fma4s<0x7E, "vfnmsubss", ssmem>;
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defm VFNMSUBSD4 : fma4s<0x7F, "vfnmsubsd", sdmem>;
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defm VFNMSUBSS4 : fma4s<0x7E, "vfnmsubss", ssmem, sse_load_f32,
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int_x86_fma4_vfnmsub_ss>;
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defm VFNMSUBSD4 : fma4s<0x7F, "vfnmsubsd", sdmem, sse_load_f64,
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int_x86_fma4_vfnmsub_sd>;
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defm VFNMSUBPS4 : fma4p<0x7C, "vfnmsubps", int_x86_fma4_vfnmsub_ps,
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int_x86_fma4_vfnmsub_ps_256, memopv4f32, memopv8f32>;
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defm VFNMSUBPD4 : fma4p<0x7D, "vfnmsubpd", int_x86_fma4_vfnmsub_pd,
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@ -191,88 +203,3 @@ let isAsmParserOnly = 1 in {
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defm VFMSUBADDPD4 : fma4p<0x5F, "vfmsubaddpd", int_x86_fma4_vfmsubadd_pd,
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int_x86_fma4_vfmsubadd_pd_256, memopv2f64, memopv4f64>;
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}
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// FMA4 Intrinsics patterns
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let Predicates = [HasFMA4] in {
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// VFMADD
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def : Pat<(int_x86_fma4_vfmadd_ss VR128:$src1, VR128:$src2, VR128:$src3),
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(VFMADDSS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfmadd_ss VR128:$src1, VR128:$src2, sse_load_f32:$src3),
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(VFMADDSS4rm VR128:$src1, VR128:$src2, sse_load_f32:$src3)>;
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def : Pat<(int_x86_fma4_vfmadd_ss VR128:$src1, sse_load_f32:$src2, VR128:$src3),
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(VFMADDSS4mr VR128:$src1, sse_load_f32:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfmadd_sd VR128:$src1, VR128:$src2, VR128:$src3),
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(VFMADDSD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfmadd_sd VR128:$src1, VR128:$src2, sse_load_f64:$src3),
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(VFMADDSD4rm VR128:$src1, VR128:$src2, sse_load_f64:$src3)>;
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def : Pat<(int_x86_fma4_vfmadd_sd VR128:$src1, sse_load_f64:$src2, VR128:$src3),
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(VFMADDSD4mr VR128:$src1, sse_load_f64:$src2, VR128:$src3)>;
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// VFMSUB
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def : Pat<(int_x86_fma4_vfmsub_ss VR128:$src1, VR128:$src2, VR128:$src3),
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(VFMSUBSS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfmsub_ss VR128:$src1, VR128:$src2, sse_load_f32:$src3),
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(VFMSUBSS4rm VR128:$src1, VR128:$src2, sse_load_f32:$src3)>;
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def : Pat<(int_x86_fma4_vfmsub_ss VR128:$src1, sse_load_f32:$src2, VR128:$src3),
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(VFMSUBSS4mr VR128:$src1, sse_load_f32:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfmsub_sd VR128:$src1, VR128:$src2, VR128:$src3),
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(VFMSUBSD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfmsub_sd VR128:$src1, VR128:$src2, sse_load_f64:$src3),
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(VFMSUBSD4rm VR128:$src1, VR128:$src2, sse_load_f64:$src3)>;
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def : Pat<(int_x86_fma4_vfmsub_sd VR128:$src1, sse_load_f64:$src2, VR128:$src3),
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(VFMSUBSD4mr VR128:$src1, sse_load_f64:$src2, VR128:$src3)>;
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// VFNMADD
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def : Pat<(int_x86_fma4_vfnmadd_ss VR128:$src1, VR128:$src2, VR128:$src3),
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(VFNMADDSS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfnmadd_ss VR128:$src1, VR128:$src2, sse_load_f32:$src3),
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(VFNMADDSS4rm VR128:$src1, VR128:$src2, sse_load_f32:$src3)>;
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def : Pat<(int_x86_fma4_vfnmadd_ss VR128:$src1, sse_load_f32:$src2, VR128:$src3),
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(VFNMADDSS4mr VR128:$src1, sse_load_f32:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfnmadd_sd VR128:$src1, VR128:$src2, VR128:$src3),
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(VFNMADDSD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfnmadd_sd VR128:$src1, VR128:$src2, sse_load_f64:$src3),
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(VFNMADDSD4rm VR128:$src1, VR128:$src2, sse_load_f64:$src3)>;
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def : Pat<(int_x86_fma4_vfnmadd_sd VR128:$src1, sse_load_f64:$src2, VR128:$src3),
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(VFNMADDSD4mr VR128:$src1, sse_load_f64:$src2, VR128:$src3)>;
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// VFNMSUB
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def : Pat<(int_x86_fma4_vfnmsub_ss VR128:$src1, VR128:$src2, VR128:$src3),
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(VFNMSUBSS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfnmsub_ss VR128:$src1, VR128:$src2, sse_load_f32:$src3),
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(VFNMSUBSS4rm VR128:$src1, VR128:$src2, sse_load_f32:$src3)>;
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def : Pat<(int_x86_fma4_vfnmsub_ss VR128:$src1, sse_load_f32:$src2, VR128:$src3),
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(VFNMSUBSS4mr VR128:$src1, sse_load_f32:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfnmsub_sd VR128:$src1, VR128:$src2, VR128:$src3),
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(VFNMSUBSD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfnmsub_sd VR128:$src1, VR128:$src2, sse_load_f64:$src3),
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(VFNMSUBSD4rm VR128:$src1, VR128:$src2, sse_load_f64:$src3)>;
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def : Pat<(int_x86_fma4_vfnmsub_sd VR128:$src1, sse_load_f64:$src2, VR128:$src3),
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(VFNMSUBSD4mr VR128:$src1, sse_load_f64:$src2, VR128:$src3)>;
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// VFMADDSUB
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def : Pat<(int_x86_fma4_vfmaddsub_ps VR128:$src1, (memopv4f32 addr:$src2),
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VR128:$src3),
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(VFMADDSUBPS4mr VR128:$src1, addr:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfmaddsub_pd VR128:$src1, (memopv2f64 addr:$src2),
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VR128:$src3),
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(VFMADDSUBPD4mr VR128:$src1, addr:$src2, VR128:$src3)>;
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// VFMSUBADD
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def : Pat<(int_x86_fma4_vfmsubadd_ps VR128:$src1, (memopv4f32 addr:$src2),
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VR128:$src3),
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(VFMSUBADDPS4mr VR128:$src1, addr:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfmsubadd_pd VR128:$src1, (memopv2f64 addr:$src2),
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VR128:$src3),
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(VFMSUBADDPD4mr VR128:$src1, addr:$src2, VR128:$src3)>;
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} // Predicates = [HasFMA4]
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