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Add support for encoding 2-register NEON instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106891 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -139,7 +139,8 @@ namespace {
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void emitMiscInstruction(const MachineInstr &MI);
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void emitNEON1RegModImm(const MachineInstr &MI);
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void emitNEON1RegModImmInstruction(const MachineInstr &MI);
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void emitNEON2RegInstruction(const MachineInstr &MI);
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/// getMachineOpValue - Return binary encoding of operand. If the machine
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/// operand requires relocation, record the relocation and return zero.
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@ -412,7 +413,10 @@ void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
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break;
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// NEON instructions.
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case ARMII::N1RegModImmFrm:
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emitNEON1RegModImm(MI);
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emitNEON1RegModImmInstruction(MI);
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break;
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case ARMII::N2RegFrm:
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emitNEON2RegInstruction(MI);
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break;
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}
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MCE.processDebugLoc(MI.getDebugLoc(), false);
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@ -1555,7 +1559,16 @@ static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
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return Binary;
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}
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void ARMCodeEmitter::emitNEON1RegModImm(const MachineInstr &MI) {
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static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
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unsigned RegM = MI.getOperand(OpIdx).getReg();
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unsigned Binary = 0;
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RegM = ARMRegisterInfo::getRegisterNumbering(RegM);
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Binary |= (RegM & 0xf);
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Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
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return Binary;
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}
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void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
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unsigned Binary = getBinaryCodeForInstr(MI);
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// Destination register is encoded in Dd.
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Binary |= encodeNEONRd(MI, 0);
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@ -1574,4 +1587,13 @@ void ARMCodeEmitter::emitNEON1RegModImm(const MachineInstr &MI) {
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emitWordLE(Binary);
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}
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void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
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unsigned Binary = getBinaryCodeForInstr(MI);
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// Destination register is encoded in Dd.
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Binary |= encodeNEONRd(MI, 0);
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Binary |= encodeNEONRm(MI, 1);
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// FIXME: This does not handle VDUPfdf or VDUPfqf.
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emitWordLE(Binary);
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}
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#include "ARMGenCodeEmitter.inc"
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