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Revert r140731, "Define classes for unary and binary FP instructions and use them to define"
It broke the unit tests. Please reapply with tests fixed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140735 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
parent
9b88d2d782
commit
5cd4ee7770
@ -64,62 +64,54 @@ def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">;
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//
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// A set of multiclasses is used to address the register usage.
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//
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// S - single precision in 16 32bit even fp registers
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// S32 - single precision in 16 32bit even fp registers
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// single precision in 32 32bit fp registers in SingleOnly mode
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// S64 - single precision in 32 64bit fp registers (In64BitMode)
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// D32 - double precision in 16 32bit even fp registers
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// D64 - double precision in 32 64bit fp registers (In64BitMode)
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//
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// Only S and D32 are supported right now.
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// Only S32 and D32 are supported right now.
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//===----------------------------------------------------------------------===//
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// Unary instruction without pattern.
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class FFR1<bits<6> funct, bits<5> fmt, RegisterClass RCDst,
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RegisterClass RCSrc, string asmstr>:
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FFR<0x11, funct, fmt, (outs RCDst:$fd), (ins RCSrc:$fs),
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!strconcat(asmstr, "\t$fd, $fs"), []> {
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let ft = 0;
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}
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// Unary instruction with pattern.
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// All operands belong to the same register class.
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class FFR1P<bits<6> funct, bits<5> fmt, RegisterClass RC, string asmstr,
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SDNode FOp>:
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FFR1<funct, fmt, RC, RC, asmstr> {
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let Pattern = [(set RC:$fd, (FOp RC:$fs))];
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}
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// Binary instruction with pattern.
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// All operands belong to the same register class.
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class FFR2<bits<6> funct, bits<5> fmt, RegisterClass RC, string asmstr,
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SDNode FOp, bit isComm = 0>:
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FFR<0x11, funct, fmt, (outs RC:$fd), (ins RC:$fs, RC:$ft),
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!strconcat(asmstr, "\t$fd, $fs, $ft"),
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[(set RC:$fd, (FOp RC:$fs, RC:$ft))]> {
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let isCommutable = isComm;
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}
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// Multiclasses.
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// Unary instruction without pattern.
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multiclass FFR1_1<bits<6> funct, string asmstr>
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{
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def _S : FFR1<funct, 16, FGR32, FGR32, asmstr>;
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def _D32 : FFR1<funct, 17, FGR32, AFGR64, asmstr>, Requires<[NotFP64bit]>;
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def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), (ins FGR32:$fs),
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!strconcat(asmstr, ".s\t$fd, $fs"), []>;
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def _D32 : FFR<0x11, funct, 0x1, (outs FGR32:$fd), (ins AFGR64:$fs),
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!strconcat(asmstr, ".d\t$fd, $fs"), []>, Requires<[NotFP64bit]>;
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}
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// Unary instruction with pattern.
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// All operands belong to the same register class.
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multiclass FFR1_2<bits<6> funct, string asmstr, SDNode FOp>
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{
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def _S : FFR1P<funct, 16, FGR32, asmstr, FOp>;
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def _D32 : FFR1P<funct, 17, AFGR64, asmstr, FOp>, Requires<[NotFP64bit]>;
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def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), (ins FGR32:$fs),
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!strconcat(asmstr, ".s\t$fd, $fs"),
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[(set FGR32:$fd, (FOp FGR32:$fs))]>;
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def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd), (ins AFGR64:$fs),
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!strconcat(asmstr, ".d\t$fd, $fs"),
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[(set AFGR64:$fd, (FOp AFGR64:$fs))]>, Requires<[NotFP64bit]>;
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}
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// Binary instruction with pattern.
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// All operands belong to the same register class.
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class FFR1_3<bits<6> funct, bits<5> fmt, RegisterClass RcSrc,
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RegisterClass RcDst, string asmstr>:
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FFR<0x11, funct, fmt, (outs RcSrc:$fd), (ins RcDst:$fs),
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!strconcat(asmstr, "\t$fd, $fs"), []>;
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multiclass FFR1_4<bits<6> funct, string asmstr, SDNode FOp, bit isComm = 0> {
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def _S : FFR2<funct, 16, FGR32, asmstr, FOp, isComm>;
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def _D32 : FFR2<funct, 17, AFGR64, asmstr, FOp, isComm>,
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Requires<[NotFP64bit]>;
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let isCommutable = isComm in {
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def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd),
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(ins FGR32:$fs, FGR32:$ft),
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!strconcat(asmstr, ".s\t$fd, $fs, $ft"),
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[(set FGR32:$fd, (FOp FGR32:$fs, FGR32:$ft))]>;
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def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd),
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(ins AFGR64:$fs, AFGR64:$ft),
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!strconcat(asmstr, ".d\t$fd, $fs, $ft"),
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[(set AFGR64:$fd, (FOp AFGR64:$fs, AFGR64:$ft))]>,
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Requires<[NotFP64bit]>;
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}
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}
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//===----------------------------------------------------------------------===//
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@ -138,37 +130,37 @@ let ft = 0 in {
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defm FSQRT : FFR1_2<0b000100, "sqrt", fsqrt>;
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/// Convert to Single Precison
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def CVTS_W32 : FFR1<0b100000, 0x2, FGR32, FGR32, "cvt.s.w">;
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def CVTS_W32 : FFR1_3<0b100000, 0x2, FGR32, FGR32, "cvt.s.w">;
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let Predicates = [IsNotSingleFloat] in {
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/// Ceil to long signed integer
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def CEIL_LS : FFR1<0b001010, 0x0, FGR32, FGR32, "ceil.l">;
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def CEIL_LD : FFR1<0b001010, 0x1, AFGR64, AFGR64, "ceil.l">;
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def CEIL_LS : FFR1_3<0b001010, 0x0, FGR32, FGR32, "ceil.l">;
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def CEIL_LD : FFR1_3<0b001010, 0x1, AFGR64, AFGR64, "ceil.l">;
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/// Round to long signed integer
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def ROUND_LS : FFR1<0b001000, 0x0, FGR32, FGR32, "round.l">;
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def ROUND_LD : FFR1<0b001000, 0x1, AFGR64, AFGR64, "round.l">;
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def ROUND_LS : FFR1_3<0b001000, 0x0, FGR32, FGR32, "round.l">;
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def ROUND_LD : FFR1_3<0b001000, 0x1, AFGR64, AFGR64, "round.l">;
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/// Floor to long signed integer
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def FLOOR_LS : FFR1<0b001011, 0x0, FGR32, FGR32, "floor.l">;
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def FLOOR_LD : FFR1<0b001011, 0x1, AFGR64, AFGR64, "floor.l">;
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def FLOOR_LS : FFR1_3<0b001011, 0x0, FGR32, FGR32, "floor.l">;
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def FLOOR_LD : FFR1_3<0b001011, 0x1, AFGR64, AFGR64, "floor.l">;
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/// Trunc to long signed integer
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def TRUNC_LS : FFR1<0b001001, 0x0, FGR32, FGR32, "trunc.l">;
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def TRUNC_LD : FFR1<0b001001, 0x1, AFGR64, AFGR64, "trunc.l">;
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def TRUNC_LS : FFR1_3<0b001001, 0x0, FGR32, FGR32, "trunc.l">;
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def TRUNC_LD : FFR1_3<0b001001, 0x1, AFGR64, AFGR64, "trunc.l">;
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/// Convert to long signed integer
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def CVTL_S : FFR1<0b100101, 0x0, FGR32, FGR32, "cvt.l">;
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def CVTL_D : FFR1<0b100101, 0x1, AFGR64, AFGR64, "cvt.l">;
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def CVTL_S : FFR1_3<0b100101, 0x0, FGR32, FGR32, "cvt.l">;
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def CVTL_D : FFR1_3<0b100101, 0x1, AFGR64, AFGR64, "cvt.l">;
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/// Convert to Double Precison
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def CVTD_S : FFR1<0b100001, 0x0, AFGR64, FGR32, "cvt.d.s">;
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def CVTD_W32 : FFR1<0b100001, 0x2, AFGR64, FGR32, "cvt.d.w">;
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def CVTD_L32 : FFR1<0b100001, 0x3, AFGR64, AFGR64, "cvt.d.l">;
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def CVTD_S32 : FFR1_3<0b100001, 0x0, AFGR64, FGR32, "cvt.d.s">;
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def CVTD_W32 : FFR1_3<0b100001, 0x2, AFGR64, FGR32, "cvt.d.w">;
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def CVTD_L32 : FFR1_3<0b100001, 0x3, AFGR64, AFGR64, "cvt.d.l">;
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/// Convert to Single Precison
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def CVTS_D32 : FFR1<0b100000, 0x1, FGR32, AFGR64, "cvt.s.d">;
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def CVTS_L32 : FFR1<0b100000, 0x3, FGR32, AFGR64, "cvt.s.l">;
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def CVTS_D32 : FFR1_3<0b100000, 0x1, FGR32, AFGR64, "cvt.s.d">;
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def CVTS_L32 : FFR1_3<0b100000, 0x3, FGR32, AFGR64, "cvt.s.l">;
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}
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}
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@ -193,7 +185,7 @@ let fd = 0 in {
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[(set FGR32:$fs, (bitconvert CPURegs:$rt))]>;
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}
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def FMOV_S : FFR<0x11, 0b000110, 0x0, (outs FGR32:$fd), (ins FGR32:$fs),
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def FMOV_S32 : FFR<0x11, 0b000110, 0x0, (outs FGR32:$fd), (ins FGR32:$fs),
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"mov.s\t$fd, $fs", []>;
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def FMOV_D32 : FFR<0x11, 0b000110, 0x1, (outs AFGR64:$fd), (ins AFGR64:$fs),
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"mov.d\t$fd, $fs", []>;
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@ -260,7 +252,7 @@ def MIPS_FCOND_NGT : PatLeaf<(i32 15)>;
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/// Floating Point Compare
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let Defs=[FCR31] in {
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def FCMP_S : FCC<0x0, (outs), (ins FGR32:$fs, FGR32:$ft, condcode:$cc),
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def FCMP_S32 : FCC<0x0, (outs), (ins FGR32:$fs, FGR32:$ft, condcode:$cc),
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"c.$cc.s\t$fs, $ft",
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[(MipsFPCmp FGR32:$fs, FGR32:$ft, imm:$cc)]>;
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@ -358,16 +350,16 @@ def fpimm0neg : PatLeaf<(fpimm), [{
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}]>;
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def : Pat<(f32 fpimm0), (MTC1 ZERO)>;
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def : Pat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
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def : Pat<(f32 fpimm0neg), (FNEG_S32 (MTC1 ZERO))>;
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def : Pat<(f32 (sint_to_fp CPURegs:$src)), (CVTS_W32 (MTC1 CPURegs:$src))>;
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def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVTD_W32 (MTC1 CPURegs:$src))>;
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def : Pat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S FGR32:$src))>;
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def : Pat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S32 FGR32:$src))>;
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def : Pat<(i32 (fp_to_sint AFGR64:$src)), (MFC1 (TRUNC_W_D32 AFGR64:$src))>;
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let Predicates = [NotFP64bit] in {
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def : Pat<(f32 (fround AFGR64:$src)), (CVTS_D32 AFGR64:$src)>;
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def : Pat<(f64 (fextend FGR32:$src)), (CVTD_S FGR32:$src)>;
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def : Pat<(f64 (fextend FGR32:$src)), (CVTD_S32 FGR32:$src)>;
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}
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@ -141,7 +141,7 @@ copyPhysReg(MachineBasicBlock &MBB,
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}
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if (Mips::FGR32RegClass.contains(DestReg, SrcReg)) {
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BuildMI(MBB, I, DL, get(Mips::FMOV_S), DestReg)
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BuildMI(MBB, I, DL, get(Mips::FMOV_S32), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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return;
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}
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