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Remove the remaining uses of abs64 and nuke it.
std::abs works just fine and we're already using it in many places. NFC intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231696 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -604,13 +604,6 @@ inline uint64_t OffsetToAlignment(uint64_t Value, uint64_t Align) {
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return RoundUpToAlignment(Value, Align) - Value;
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}
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/// abs64 - absolute value of a 64-bit int. Not all environments support
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/// "abs" on whatever their name for the 64-bit int type is. The absolute
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/// value of the largest negative number is undefined, as with "abs".
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inline int64_t abs64(int64_t x) {
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return (x < 0) ? -x : x;
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}
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/// SignExtend32 - Sign extend B-bit number x to 32-bit int.
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/// Usage int32_t r = SignExtend32<5>(x);
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template <unsigned B> inline int32_t SignExtend32(uint32_t x) {
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@ -10310,9 +10310,9 @@ bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
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bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
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// Thumb2 and ARM modes can use cmn for negative immediates.
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if (!Subtarget->isThumb())
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return ARM_AM::getSOImmVal(llvm::abs64(Imm)) != -1;
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return ARM_AM::getSOImmVal(std::abs(Imm)) != -1;
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if (Subtarget->isThumb2())
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return ARM_AM::getT2SOImmVal(llvm::abs64(Imm)) != -1;
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return ARM_AM::getT2SOImmVal(std::abs(Imm)) != -1;
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// Thumb1 doesn't have cmn, and only 8-bit immediates.
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return Imm >= 0 && Imm <= 255;
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}
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@ -10323,7 +10323,7 @@ bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
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/// immediate into a register.
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bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {
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// Same encoding for add/sub, just flip the sign.
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int64_t AbsImm = llvm::abs64(Imm);
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int64_t AbsImm = std::abs(Imm);
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if (!Subtarget->isThumb())
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return ARM_AM::getSOImmVal(AbsImm) != -1;
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if (Subtarget->isThumb2())
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@ -690,7 +690,7 @@ CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop,
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// If the induction variable bump is not a power of 2, quit.
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// Othwerise we'd need a general integer division.
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if (!isPowerOf2_64(abs64(IVBump)))
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if (!isPowerOf2_64(std::abs(IVBump)))
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return nullptr;
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MachineBasicBlock *PH = Loop->getLoopPreheader();
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@ -192,7 +192,7 @@ bool PPCLoopDataPrefetch::runOnLoop(Loop *L) {
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const SCEV *PtrDiff = SE->getMinusSCEV(LSCEVAddRec, K->second);
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if (const SCEVConstant *ConstPtrDiff =
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dyn_cast<SCEVConstant>(PtrDiff)) {
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int64_t PD = abs64(ConstPtrDiff->getValue()->getSExtValue());
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int64_t PD = std::abs(ConstPtrDiff->getValue()->getSExtValue());
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if (PD < (int64_t) CacheLineSize) {
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DupPref = true;
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break;
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@ -124,7 +124,7 @@ static unsigned getNewAlignmentDiff(const SCEV *DiffSCEV,
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// If the displacement is not an exact multiple, but the remainder is a
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// constant, then return this remainder (but only if it is a power of 2).
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uint64_t DiffUnitsAbs = abs64(DiffUnits);
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uint64_t DiffUnitsAbs = std::abs(DiffUnits);
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if (isPowerOf2_64(DiffUnitsAbs))
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return (unsigned) DiffUnitsAbs;
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}
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@ -3825,7 +3825,7 @@ void LSRInstance::GenerateCrossUseConstantOffsets() {
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if (C->getValue()->isNegative() !=
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(NewF.BaseOffset < 0) &&
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(C->getValue()->getValue().abs() * APInt(BitWidth, F.Scale))
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.ule(abs64(NewF.BaseOffset)))
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.ule(std::abs(NewF.BaseOffset)))
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continue;
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// OK, looks good.
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@ -3856,7 +3856,7 @@ void LSRInstance::GenerateCrossUseConstantOffsets() {
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J != JE; ++J)
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if (const SCEVConstant *C = dyn_cast<SCEVConstant>(*J))
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if ((C->getValue()->getValue() + NewF.BaseOffset).abs().slt(
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abs64(NewF.BaseOffset)) &&
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std::abs(NewF.BaseOffset)) &&
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(C->getValue()->getValue() +
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NewF.BaseOffset).countTrailingZeros() >=
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countTrailingZeros<uint64_t>(NewF.BaseOffset))
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@ -649,11 +649,11 @@ namespace {
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if (VTy != VTy2 && Offset < 0) {
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int64_t VTy2TSS = (int64_t) DL->getTypeStoreSize(VTy2);
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OffsetInElmts = Offset/VTy2TSS;
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return (abs64(Offset) % VTy2TSS) == 0;
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return (std::abs(Offset) % VTy2TSS) == 0;
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}
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OffsetInElmts = Offset/VTyTSS;
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return (abs64(Offset) % VTyTSS) == 0;
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return (std::abs(Offset) % VTyTSS) == 0;
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}
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return false;
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@ -984,8 +984,8 @@ namespace {
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unsigned IAlignment, JAlignment, IAddressSpace, JAddressSpace;
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int64_t OffsetInElmts = 0;
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if (getPairPtrInfo(I, J, IPtr, JPtr, IAlignment, JAlignment,
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IAddressSpace, JAddressSpace,
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OffsetInElmts) && abs64(OffsetInElmts) == 1) {
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IAddressSpace, JAddressSpace, OffsetInElmts) &&
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std::abs(OffsetInElmts) == 1) {
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FixedOrder = (int) OffsetInElmts;
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unsigned BottomAlignment = IAlignment;
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if (OffsetInElmts < 0) BottomAlignment = JAlignment;
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