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[mips] Align the stack to 16-bytes for mfp64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193641 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -30,10 +30,12 @@ def MipsInstrInfo : InstrInfo;
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// Mips Subtarget features //
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//===----------------------------------------------------------------------===//
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def StackAlign16 : SubtargetFeature<"stackalign16", "StackAlignment", "16",
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"Set stack alignment to 16-bytes.">;
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def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
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"General Purpose Registers are 64-bit wide.">;
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def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
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"Support 64-bit FP registers.">;
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"Support 64-bit FP registers.", [StackAlign16]>;
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def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
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"true", "Only supports single precision float">;
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def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32",
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@ -20,7 +20,7 @@ namespace llvm {
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class Mips16FrameLowering : public MipsFrameLowering {
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public:
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explicit Mips16FrameLowering(const MipsSubtarget &STI)
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: MipsFrameLowering(STI, 8) {}
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: MipsFrameLowering(STI, STI.stackAlignment()) {}
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/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
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/// the function.
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@ -21,7 +21,7 @@ namespace llvm {
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class MipsSEFrameLowering : public MipsFrameLowering {
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public:
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explicit MipsSEFrameLowering(const MipsSubtarget &STI)
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: MipsFrameLowering(STI, STI.hasMips64() ? 16 : 8) {}
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: MipsFrameLowering(STI, STI.stackAlignment()) {}
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/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
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/// the function.
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@ -72,7 +72,7 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
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InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
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InMicroMipsMode(false), HasDSP(false), HasDSPR2(false),
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AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false),
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RM(_RM), OverrideMode(NoOverride), TM(_TM)
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StackAlignment(8), RM(_RM), OverrideMode(NoOverride), TM(_TM)
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{
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std::string CPUName = CPU;
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if (CPUName.empty())
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@ -116,6 +116,8 @@ protected:
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// HasMSA -- supports MSA ASE.
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bool HasMSA;
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unsigned StackAlignment;
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InstrItineraryData InstrItins;
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// The instance to the register info section object
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@ -216,6 +218,9 @@ public:
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// really use them if in addition we are in mips16 mode
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//
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static bool useConstantIslands();
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unsigned stackAlignment() const { return StackAlignment; }
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// Grab MipsRegInfo object
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const MipsReginfo &getMReginfo() const { return MRI; }
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14
test/CodeGen/Mips/stack-alignment.ll
Normal file
14
test/CodeGen/Mips/stack-alignment.ll
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@ -0,0 +1,14 @@
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; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=32
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; RUN: llc -march=mipsel -mattr=+fp64 < %s | FileCheck %s -check-prefix=32-FP64
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; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=64
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; 32: addiu $sp, $sp, -8
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; 32-FP64: addiu $sp, $sp, -16
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; 64: addiu $sp, $sp, -16
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define i32 @foo1() #0 {
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entry:
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ret i32 14
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}
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attributes #0 = { "no-frame-pointer-elim"="true" }
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