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Add 64-bit load and store instructions.
There is only a few new instructions, the rest is handled with patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178528 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
parent
73c5f80ec9
commit
61ed5ddefe
@ -171,3 +171,71 @@ def : Pat<(add i64:$a, (i64 simm13:$b)), (ADDri $a, (as_i32imm $b))>;
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def : Pat<(sub i64:$a, (i64 simm13:$b)), (SUBri $a, (as_i32imm $b))>;
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} // Predicates = [Is64Bit]
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//===----------------------------------------------------------------------===//
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// 64-bit Loads and Stores.
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//===----------------------------------------------------------------------===//
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//
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// All the 32-bit loads and stores are available. The extending loads are sign
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// or zero-extending to 64 bits. The LDrr and LDri instructions load 32 bits
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// zero-extended to i64. Their mnemonic is lduw in SPARC v9 (Load Unsigned
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// Word).
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//
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// SPARC v9 adds 64-bit loads as well as a sign-extending ldsw i32 loads.
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let Predicates = [Is64Bit] in {
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// 64-bit loads.
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def LDXrr : F3_1<3, 0b001011,
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(outs I64Regs:$dst), (ins MEMrr:$addr),
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"ldx [$addr], $dst",
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[(set i64:$dst, (load ADDRrr:$addr))]>;
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def LDXri : F3_2<3, 0b001011,
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(outs I64Regs:$dst), (ins MEMri:$addr),
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"ldx [$addr], $dst",
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[(set i64:$dst, (load ADDRri:$addr))]>;
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// Extending loads to i64.
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def : Pat<(i64 (zextloadi8 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>;
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def : Pat<(i64 (zextloadi8 ADDRri:$addr)), (LDUBri ADDRri:$addr)>;
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def : Pat<(i64 (sextloadi8 ADDRrr:$addr)), (LDSBrr ADDRrr:$addr)>;
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def : Pat<(i64 (sextloadi8 ADDRri:$addr)), (LDSBri ADDRri:$addr)>;
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def : Pat<(i64 (zextloadi16 ADDRrr:$addr)), (LDUHrr ADDRrr:$addr)>;
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def : Pat<(i64 (zextloadi16 ADDRri:$addr)), (LDUHri ADDRri:$addr)>;
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def : Pat<(i64 (sextloadi16 ADDRrr:$addr)), (LDSHrr ADDRrr:$addr)>;
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def : Pat<(i64 (sextloadi16 ADDRri:$addr)), (LDSHri ADDRri:$addr)>;
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def : Pat<(i64 (zextloadi32 ADDRrr:$addr)), (LDrr ADDRrr:$addr)>;
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def : Pat<(i64 (zextloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>;
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// Sign-extending load of i32 into i64 is a new SPARC v9 instruction.
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def LDSWrr : F3_1<3, 0b001011,
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(outs I64Regs:$dst), (ins MEMrr:$addr),
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"ldsw [$addr], $dst",
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[(set i64:$dst, (sextloadi32 ADDRrr:$addr))]>;
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def LDSWri : F3_2<3, 0b001011,
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(outs I64Regs:$dst), (ins MEMri:$addr),
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"ldsw [$addr], $dst",
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[(set i64:$dst, (sextloadi32 ADDRri:$addr))]>;
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// 64-bit stores.
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def STXrr : F3_1<3, 0b001110,
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(outs), (ins MEMrr:$addr, I64Regs:$src),
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"stx $src, [$addr]",
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[(store i64:$src, ADDRrr:$addr)]>;
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def STXri : F3_2<3, 0b001110,
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(outs), (ins MEMri:$addr, I64Regs:$src),
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"stx $src, [$addr]",
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[(store i64:$src, ADDRri:$addr)]>;
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// Truncating stores from i64 are identical to the i32 stores.
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def : Pat<(truncstorei8 i64:$src, ADDRrr:$addr), (STBrr ADDRrr:$addr, $src)>;
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def : Pat<(truncstorei8 i64:$src, ADDRri:$addr), (STBri ADDRri:$addr, $src)>;
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def : Pat<(truncstorei16 i64:$src, ADDRrr:$addr), (STHrr ADDRrr:$addr, $src)>;
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def : Pat<(truncstorei16 i64:$src, ADDRri:$addr), (STHri ADDRri:$addr, $src)>;
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def : Pat<(truncstorei32 i64:$src, ADDRrr:$addr), (STrr ADDRrr:$addr, $src)>;
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def : Pat<(truncstorei32 i64:$src, ADDRri:$addr), (STri ADDRri:$addr, $src)>;
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} // Predicates = [Is64Bit]
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@ -86,3 +86,61 @@ define i64 @reg_imm_alu(i64 %x, i64 %y, i64 %z) {
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%b = xor i64 %a, 2
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ret i64 %b
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}
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; CHECK: loads
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; CHECK: ldx [%i0]
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; CHECK: stx %
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; CHECK: ld [%i1]
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; CHECK: st %
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; CHECK: ldsw [%i2]
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; CHECK: stx %
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; CHECK: ldsh [%i3]
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; CHECK: sth %
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define i64 @loads(i64* %p, i32* %q, i32* %r, i16* %s) {
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%a = load i64* %p
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%ai = add i64 1, %a
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store i64 %ai, i64* %p
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%b = load i32* %q
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%b2 = zext i32 %b to i64
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%bi = trunc i64 %ai to i32
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store i32 %bi, i32* %q
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%c = load i32* %r
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%c2 = sext i32 %c to i64
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store i64 %ai, i64* %p
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%d = load i16* %s
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%d2 = sext i16 %d to i64
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%di = trunc i64 %ai to i16
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store i16 %di, i16* %s
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%x1 = add i64 %a, %b2
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%x2 = add i64 %c2, %d2
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%x3 = add i64 %x1, %x2
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ret i64 %x3
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}
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; CHECK: stores
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; CHECK: ldx [%i0+8], [[R:%[goli][0-7]]]
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; CHECK: stx [[R]], [%i0+16]
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; CHECK: st [[R]], [%i1+-8]
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; CHECK: sth [[R]], [%i2+40]
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; CHECK: stb [[R]], [%i3+-20]
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define void @stores(i64* %p, i32* %q, i16* %r, i8* %s) {
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%p1 = getelementptr i64* %p, i64 1
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%p2 = getelementptr i64* %p, i64 2
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%pv = load i64* %p1
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store i64 %pv, i64* %p2
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%q2 = getelementptr i32* %q, i32 -2
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%qv = trunc i64 %pv to i32
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store i32 %qv, i32* %q2
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%r2 = getelementptr i16* %r, i16 20
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%rv = trunc i64 %pv to i16
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store i16 %rv, i16* %r2
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%s2 = getelementptr i8* %s, i8 -20
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%sv = trunc i64 %pv to i8
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store i8 %sv, i8* %s2
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ret void
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}
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