mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-04 06:09:05 +00:00
MIPS DSP: Add predicates and instruction template.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164434 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
b430cecc0e
commit
67032b27cd
25
lib/Target/Mips/MipsDSPInstrFormats.td
Normal file
25
lib/Target/Mips/MipsDSPInstrFormats.td
Normal file
@ -0,0 +1,25 @@
|
||||
//===- MipsDSPInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def HasDSP : Predicate<"Subtarget.hasDSP()">,
|
||||
AssemblerPredicate<"FeatureDSP">;
|
||||
def HasDSPR2 : Predicate<"Subtarget.hasDSPR2()">,
|
||||
AssemblerPredicate<"FeatureDSPR2">;
|
||||
|
||||
// Fields.
|
||||
class Field6<bits<6> val> {
|
||||
bits<6> V = val;
|
||||
}
|
||||
|
||||
def SPECIAL3_OPCODE : Field6<0b011111>;
|
||||
def REGIMM_OPCODE : Field6<0b000001>;
|
||||
|
||||
class DSPInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
|
||||
let Predicates = [HasDSP];
|
||||
}
|
Loading…
Reference in New Issue
Block a user