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Add support for a few simple fixups to the ARM Darwin asm backend. This allows

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constant pool references and global variable refernces to resolve properly
for object file generation. For example,

int x;
void foo(unsigned a, unsigned *p) {
  p[a] = x;
}

can now be successfully compiled directly to an (ARM mode) object file.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118469 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-11-09 01:37:15 +00:00
parent 71365d3774
commit 679cbd3b21
2 changed files with 36 additions and 10 deletions
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36
lib/Target/ARM/ARMAsmBackend.cpp
View File

@ -9,7 +9,7 @@
#include "llvm/Target/TargetAsmBackend.h"
#include "ARM.h"
//FIXME: add #include "ARMFixupKinds.h"
#include "ARMFixupKinds.h"
#include "llvm/ADT/Twine.h"
#include "llvm/MC/ELFObjectWriter.h"
#include "llvm/MC/MCAssembler.h"
@ -138,9 +138,41 @@ public:
}
};
static unsigned getFixupKindLog2Size(unsigned Kind) {
switch (Kind) {
default: llvm_unreachable("Unknown fixup kind!");
case FK_Data_4: return 2;
case ARM::fixup_arm_pcrel_12: return 2;
case ARM::fixup_arm_vfp_pcrel_12: return 1;
}
}
static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
switch (Kind) {
default:
llvm_unreachable("Unknown fixup kind!");
case FK_Data_4:
case ARM::fixup_arm_pcrel_12:
// ARM PC-relative values are offset by 8.
return Value - 8;
case ARM::fixup_arm_vfp_pcrel_12:
// The VFP ld/st immediate value doesn't encode the low two bits since
// they're always zero. Offset by 8 just as above.
return (Value - 8) >> 2;
}
}
void DarwinARMAsmBackend::ApplyFixup(const MCFixup &Fixup, MCDataFragment &DF,
uint64_t Value) const {
assert(0 && "DarwinARMAsmBackend::ApplyFixup() unimplemented");
unsigned NumBytes = getFixupKindLog2Size(Fixup.getKind());
Value = adjustFixupValue(Fixup.getKind(), Value);
assert(Fixup.getOffset() + NumBytes <= DF.getContents().size() &&
"Invalid fixup offset!");
// For each byte of the fragment that the fixup touches, mask in the
// bits from the fixup value.
for (unsigned i = 0; i != NumBytes; ++i)
DF.getContents()[Fixup.getOffset() + i] |= uint8_t(Value >> (i * 8));
}
} // end anonymous namespace

10
lib/Target/ARM/ARMMCCodeEmitter.cpp
View File

@ -234,7 +234,7 @@ getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
// If The first operand isn't a register, we have a label reference.
const MCOperand &MO = MI.getOperand(OpIdx);
if (!MO.isReg()) {
Reg = ARM::PC; // Rn is PC.
Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
Imm12 = 0;
assert(MO.isExpr() && "Unexpected machine operand type!");
@ -246,9 +246,6 @@ getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
} else
isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
if (Reg == ARM::PC)
return ARM::PC << 13; // Rn is PC;
uint32_t Binary = Imm12 & 0xfff;
// Immediate is always encoded as positive. The 'U' bit controls add vs sub.
if (isAdd)
@ -268,7 +265,7 @@ getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
// If The first operand isn't a register, we have a label reference.
const MCOperand &MO = MI.getOperand(OpIdx);
if (!MO.isReg()) {
Reg = ARM::PC; // Rn is PC.
Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
Imm8 = 0;
assert(MO.isExpr() && "Unexpected machine operand type!");
@ -280,9 +277,6 @@ getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
} else
EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
if (Reg == ARM::PC)
return ARM::PC << 9; // Rn is PC;
uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
// Immediate is always encoded as positive. The 'U' bit controls add vs sub.
if (ARM_AM::getAM5Op(Imm8) == ARM_AM::add)