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ARM clean up the imm_sr operand class representation.

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Represent the operand value as it will be encoded in the instruction. This
allows removing the specialized encoder and decoder methods entirely. Add
an assembler match class while we're at it to lay groundwork for parsing the
thumb shift instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137879 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-08-17 21:51:27 +00:00
parent 795cf5efba
commit 70939ee141
8 changed files with 36 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/ARM/ARMCodeEmitter.cpp
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@ -236,8 +236,6 @@ namespace {
const {return 0; }
uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
const { return 0; }
unsigned getThumbSRImmOpValue(const MachineInstr &MI, unsigned OpIdx)
const { return 0; }
unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
const {

14
lib/Target/ARM/ARMInstrThumb.td
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@ -19,11 +19,17 @@ def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
SDNPVariadic]>;
def imm_sr : Operand<i32>, ImmLeaf<i32, [{
def imm_sr_XFORM: SDNodeXForm<imm, [{
unsigned Imm = N->getZExtValue();
return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), MVT::i32);
}]>;
def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; }
def imm_sr : Operand<i32>, PatLeaf<(imm), [{
uint64_t Imm = N->getZExtValue();
return Imm > 0 && Imm <= 32;
}]> {
let EncoderMethod = "getThumbSRImmOpValue";
let DecoderMethod = "DecodeThumbSRImm";
}], imm_sr_XFORM> {
let PrintMethod = "printThumbSRImm";
let ParserMatchClass = ThumbSRImmAsmOperand;
}
def imm_neg_XFORM : SDNodeXForm<imm, [{

2
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -771,7 +771,7 @@ multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, PatFrag opnode> {
def ri : T2sTwoRegShiftImm<
(outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
opc, ".w\t$Rd, $Rm, $imm",
[(set rGPR:$Rd, (opnode rGPR:$Rm, ty:$imm))]> {
[(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]> {
let Inst{31-27} = 0b11101;
let Inst{26-21} = 0b010010;
let Inst{19-16} = 0b1111; // Rn

17
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -482,6 +482,14 @@ public:
int64_t Value = CE->getValue();
return Value >= 0 && Value <= 0xffffff;
}
bool isImmThumbSR() const {
if (Kind != Immediate)
return false;
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
if (!CE) return false;
int64_t Value = CE->getValue();
return Value > 0 && Value < 33;
}
bool isPKHLSLImm() const {
if (Kind != Immediate)
return false;
@ -794,6 +802,15 @@ public:
addExpr(Inst, getImm());
}
void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
// The constant encodes as the immediate, except for 32, which encodes as
// zero.
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
unsigned Imm = CE->getValue();
Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
}
void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
addExpr(Inst, getImm());

11
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -210,8 +210,6 @@ static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
@ -2474,15 +2472,6 @@ static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
return Success;
}
static DecodeStatus DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
if (Val == 0)
Inst.addOperand(MCOperand::CreateImm(32));
else
Inst.addOperand(MCOperand::CreateImm(Val));
return Success;
}
static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
DecodeStatus S = Success;

8
lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
View File

@ -639,7 +639,13 @@ void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
O << "#" << MI->getOperand(OpNum).getImm() * 4;
O << "#" << MI->getOperand(OpNum).getImm() * 4;
}
void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
unsigned Imm = MI->getOperand(OpNum).getImm();
O << "#" << (Imm == 0 ? 32 : Imm);
}
void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,

1
lib/Target/ARM/InstPrinter/ARMInstPrinter.h
View File

@ -74,6 +74,7 @@ public:
void printPKHASRShiftImm(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printThumbSRImm(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printThumbITMask(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printThumbAddrModeRROperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);

10
lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
View File

@ -443,16 +443,6 @@ EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
return isAdd;
}
uint32_t ARMMCCodeEmitter::
getThumbSRImmOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const {
const MCOperand &MO = MI.getOperand(OpIdx);
assert(MO.isImm() && "Expected constant shift!");
int val = MO.getImm();
return (val == 32) ? 0 : val;
}
/// getBranchTargetOpValue - Helper function to get the branch target operand,
/// which is either an immediate or requires a fixup.
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,