6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-06-22 10:24:26 +00:00
Code Issues Projects Releases Wiki Activity

ARM clean up the imm_sr operand class representation.

Browse Source 
Represent the operand value as it will be encoded in the instruction. This
allows removing the specialized encoder and decoder methods entirely. Add
an assembler match class while we're at it to lay groundwork for parsing the
thumb shift instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137879 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2011-08-17 21:51:27 +00:00
parent 795cf5efba
commit 70939ee141
8 changed files with 36 additions and 29 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -210,8 +210,6 @@ static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
@ -2474,15 +2472,6 @@ static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
return Success;
}
static DecodeStatus DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
if (Val == 0)
Inst.addOperand(MCOperand::CreateImm(32));
else
Inst.addOperand(MCOperand::CreateImm(Val));
return Success;
}
static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
DecodeStatus S = Success;