6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-21 02:29:22 +00:00
Code Issues Projects Releases Wiki Activity

Pseudo-ize the ARM 'B' instruction.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127510 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-03-11 23:24:15 +00:00
parent 3c5edaaf59
commit 72422d38ba
3 changed files with 14 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
lib/Target/ARM/ARMAsmPrinter.cpp
View File

@ -945,6 +945,17 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
unsigned Opc = MI->getOpcode();
switch (Opc) {
default: break;
case ARM::B: {
// B is just a Bcc with an 'always' predicate.
MCInst TmpInst;
LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
TmpInst.setOpcode(ARM::Bcc);
// Add predicate operands.
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
TmpInst.addOperand(MCOperand::CreateReg(0));
OutStreamer.EmitInstruction(TmpInst);
return;
}
case ARM::LDMIA_RET: {
// LDMIA_RET is just a normal LDMIA_UPD instruction that targets PC and as
// such has additional code-gen properties and scheduling information.

10
lib/Target/ARM/ARMInstrInfo.td
View File

@ -1485,15 +1485,11 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
}
let isBranch = 1, isTerminator = 1 in {
// B is "predicable" since it can be xformed into a Bcc.
// B is "predicable" since it's just a Bcc with an 'always' condition.
let isBarrier = 1 in {
let isPredicable = 1 in
def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
"b\t$target", [(br bb:$target)]> {
bits<24> target;
let Inst{31-28} = 0b1110;
let Inst{23-0} = target;
}
def B : ARMPseudoInst<(outs), (ins brtarget:$target), Size4Bytes, IIC_Br,
[(br bb:$target)]>;
let isNotDuplicable = 1, isIndirectBranch = 1 in {
def BR_JTr : ARMPseudoInst<(outs),

3
utils/TableGen/ARMDecoderEmitter.cpp
View File

@ -1592,9 +1592,6 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI,
// better off using the generic RSCri and RSCrs instructions.
if (Name == "RSCSri" || Name == "RSCSrs") return false;
// Bcc is in a more generic form than B. Ignore B when decoding.
if (Name == "B") return false;
// Ignore the non-Darwin BL instructions and the TPsoft (TLS) instruction.
if (Name == "BL" || Name == "BL_pred" || Name == "BLX" ||
Name == "BLX_pred" || Name == "TPsoft")