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Fix this logic.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23756 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-10-15 22:35:40 +00:00
parent 85d63bbff7
commit 750dbd5950
1 changed files with 1 additions and 1 deletions
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2
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -808,7 +808,7 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
if (ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
// If the RHS of the AND has zeros where the sign bits of the SRA will
// land, turn the SRA into an SRL.
if (MaskedValueIsZero(N1, (~0ULL << N01C->getValue()) &
if (MaskedValueIsZero(N1, (~0ULL << (OpSizeInBits-N01C->getValue())) &
(~0ULL>>(64-OpSizeInBits)), TLI)) {
WorkList.push_back(N);
CombineTo(N0.Val, DAG.getNode(ISD::SRL, VT, N0.getOperand(0),