mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-19 19:29:31 +00:00
Clean up 32/64bit and Darwin/AIX split. Next steps: 64 bit ISel, AIX asm printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15662 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
74a806cd3d
commit
7a4fe9be7e
@ -15,12 +15,18 @@
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#ifndef TARGET_POWERPC_H
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#define TARGET_POWERPC_H
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#include <iosfwd>
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namespace llvm {
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class FunctionPass;
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class TargetMachine;
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FunctionPass *createPowerPCPEI();
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FunctionPass *createPPCBranchSelectionPass();
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FunctionPass *createPPC32ISelSimple(TargetMachine &TM);
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FunctionPass *createPPC64ISelSimple(TargetMachine &TM);
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FunctionPass *createPPC32AsmPrinter(std::ostream &OS,TargetMachine &TM);
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} // end namespace llvm;
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@ -1,31 +0,0 @@
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//===-- PPC32.h - Top-level interface for 32-bit PowerPC -----------*- C++ -*-//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the entry points for global functions defined in the LLVM
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// Darwin/PowerPC back-end.
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//
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//===----------------------------------------------------------------------===//
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#ifndef TARGET_POWERPC32_H
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#define TARGET_POWERPC32_H
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#include "PowerPC.h"
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#include <iosfwd>
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namespace llvm {
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class FunctionPass;
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class TargetMachine;
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FunctionPass *createPPC32ISelSimple(TargetMachine &TM);
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FunctionPass *createPPC32AsmPrinter(std::ostream &OS,TargetMachine &TM);
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} // end namespace llvm;
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#endif
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@ -11,7 +11,6 @@
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#include "PowerPC.h"
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#include "PowerPCInstrBuilder.h"
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#include "PowerPCInstrInfo.h"
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#include "PPC32.h"
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#include "PPC32TargetMachine.h"
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#include "llvm/Constants.h"
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#include "llvm/DerivedTypes.h"
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@ -24,12 +24,6 @@ namespace llvm {
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public:
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PPC32JITInfo(TargetMachine &tm) : PowerPCJITInfo(tm) {}
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/// addPassesToJITCompile - Add passes to the specified pass manager to
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/// implement a fast dynamic compiler for this target. Return true if this
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/// is not supported for this target.
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///
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virtual void addPassesToJITCompile(FunctionPassManager &PM);
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/// replaceMachineCodeForFunction - Make it so that calling the function
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/// whose machine code is at OLD turns into a call to NEW, perhaps by
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/// overwriting OLD with a branch to NEW. This is used for self-modifying
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@ -1,115 +0,0 @@
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//===-- PowerPCTargetMachine.cpp - Define TargetMachine for PowerPC -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "PPC32.h"
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#include "PPC32JITInfo.h"
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#include "PPC32TargetMachine.h"
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#include "llvm/Module.h"
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#include "llvm/PassManager.h"
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#include "llvm/CodeGen/IntrinsicLowering.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetMachineRegistry.h"
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#include "llvm/Transforms/Scalar.h"
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#include <iostream>
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using namespace llvm;
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namespace {
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const std::string PPC32 = "Darwin/PowerPC";
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// Register the target
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RegisterTarget<PPC32TargetMachine>
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X("powerpc-darwin", " Darwin/PowerPC (experimental)");
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}
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/// PowerPCTargetMachine ctor - Create an ILP32 architecture model
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///
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PPC32TargetMachine::PPC32TargetMachine(const Module &M,
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IntrinsicLowering *IL)
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: PowerPCTargetMachine(PPC32, IL,
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TargetData(PPC32,false,4,4,4,4,4,4,2,1,4),
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TargetFrameInfo(TargetFrameInfo::StackGrowsDown,16,-4),
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PPC32JITInfo(*this)) {}
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/// addPassesToEmitAssembly - Add passes to the specified pass manager
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/// to implement a static compiler for this target.
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///
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bool PPC32TargetMachine::addPassesToEmitAssembly(PassManager &PM,
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std::ostream &Out) {
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// FIXME: Implement efficient support for garbage collection intrinsics.
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PM.add(createLowerGCPass());
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// FIXME: Implement the invoke/unwind instructions!
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PM.add(createLowerInvokePass());
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// FIXME: Implement the switch instruction in the instruction selector!
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PM.add(createLowerSwitchPass());
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PM.add(createLowerConstantExpressionsPass());
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// Make sure that no unreachable blocks are instruction selected.
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PM.add(createUnreachableBlockEliminationPass());
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PM.add(createPPC32ISelSimple(*this));
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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PM.add(createRegisterAllocator());
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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// I want a PowerPC specific prolog/epilog code inserter so I can put the
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// fills/spills in the right spots.
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PM.add(createPowerPCPEI());
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// Must run branch selection immediately preceding the printer
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PM.add(createPPCBranchSelectionPass());
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PM.add(createPPC32AsmPrinter(Out, *this));
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PM.add(createMachineCodeDeleter());
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return false;
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}
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/// addPassesToJITCompile - Add passes to the specified pass manager to
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/// implement a fast dynamic compiler for this target.
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///
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void PPC32JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
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// FIXME: Implement efficient support for garbage collection intrinsics.
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PM.add(createLowerGCPass());
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// FIXME: Implement the invoke/unwind instructions!
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PM.add(createLowerInvokePass());
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// FIXME: Implement the switch instruction in the instruction selector!
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PM.add(createLowerSwitchPass());
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PM.add(createLowerConstantExpressionsPass());
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// Make sure that no unreachable blocks are instruction selected.
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PM.add(createUnreachableBlockEliminationPass());
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PM.add(createPPC32ISelSimple(TM));
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PM.add(createRegisterAllocator());
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PM.add(createPrologEpilogCodeInserter());
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}
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unsigned PPC32TargetMachine::getModuleMatchQuality(const Module &M) {
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if (M.getEndianness() == Module::BigEndian &&
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M.getPointerSize() == Module::Pointer32)
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return 10; // Direct match
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else if (M.getEndianness() != Module::AnyEndianness ||
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M.getPointerSize() != Module::AnyPointerSize)
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return 0; // Match for some other target
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return getJITMatchQuality()/2;
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}
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@ -1,20 +0,0 @@
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//===-- PPC64.h - Top-level interface for AIX/PowerPC -------------*- C++ -*-//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the entry points for global functions defined in the LLVM
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// PowerPC 64-bit back-end.
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//
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//===----------------------------------------------------------------------===//
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#ifndef TARGET_POWERPC_AIX_H
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#define TARGET_POWERPC_AIX_H
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#include "PowerPC.h"
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#endif
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@ -23,12 +23,6 @@ namespace llvm {
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public:
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PPC64JITInfo(TargetMachine &tm) : PowerPCJITInfo(tm) {}
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/// addPassesToJITCompile - Add passes to the specified pass manager to
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/// implement a fast dynamic compiler for this target. Return true if this
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/// is not supported for this target.
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///
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virtual void addPassesToJITCompile(FunctionPassManager &PM);
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/// replaceMachineCodeForFunction - Make it so that calling the function
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/// whose machine code is at OLD turns into a call to NEW, perhaps by
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/// overwriting OLD with a branch to NEW. This is used for self-modifying
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@ -1,117 +0,0 @@
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//===-- PPC64TargetMachine.cpp - Define TargetMachine for AIX/PowerPC ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "PowerPC.h"
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#include "PPC64JITInfo.h"
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#include "PPC64TargetMachine.h"
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#include "llvm/Module.h"
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#include "llvm/PassManager.h"
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#include "llvm/CodeGen/IntrinsicLowering.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetMachineRegistry.h"
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#include "llvm/Transforms/Scalar.h"
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#include <iostream>
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using namespace llvm;
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namespace {
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const std::string PPC64 = "AIX/PowerPC";
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// Register the target
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RegisterTarget<PPC64TargetMachine>
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X("powerpc-aix", " AIX/PowerPC (experimental)");
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}
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/// PPC64TargetMachine ctor
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///
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PPC64TargetMachine::PPC64TargetMachine(const Module &M, IntrinsicLowering *IL)
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// FIXME: this is wrong!
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: PowerPCTargetMachine(PPC64, IL,
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TargetData(PPC64,false,8,4,4,4,4,4,2,1,4),
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TargetFrameInfo(TargetFrameInfo::StackGrowsDown,16,-4),
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PPC64JITInfo(*this)) {}
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/// addPassesToEmitAssembly - Add passes to the specified pass manager
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/// to implement a static compiler for this target.
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///
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bool PPC64TargetMachine::addPassesToEmitAssembly(PassManager &PM,
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std::ostream &Out) {
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// FIXME: Implement efficient support for garbage collection intrinsics.
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PM.add(createLowerGCPass());
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// FIXME: Implement the invoke/unwind instructions!
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PM.add(createLowerInvokePass());
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// FIXME: Implement the switch instruction in the instruction selector!
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PM.add(createLowerSwitchPass());
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PM.add(createLowerConstantExpressionsPass());
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// Make sure that no unreachable blocks are instruction selected.
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PM.add(createUnreachableBlockEliminationPass());
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// FIXME: instruction selector!
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//PM.add(createPPCSimpleInstructionSelector(*this));
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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PM.add(createRegisterAllocator());
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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// I want a PowerPC specific prolog/epilog code inserter so I can put the
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// fills/spills in the right spots.
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//PM.add(createPowerPCPEI());
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// Must run branch selection immediately preceding the printer
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//PM.add(createPPCBranchSelectionPass());
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//PM.add(createPPC32AsmPrinterPass(Out, *this));
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PM.add(createMachineCodeDeleter());
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return false;
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}
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/// addPassesToJITCompile - Add passes to the specified pass manager to
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/// implement a fast dynamic compiler for this target.
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///
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void PPC64JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
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// FIXME: Implement efficient support for garbage collection intrinsics.
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PM.add(createLowerGCPass());
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// FIXME: Implement the invoke/unwind instructions!
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PM.add(createLowerInvokePass());
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// FIXME: Implement the switch instruction in the instruction selector!
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PM.add(createLowerSwitchPass());
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PM.add(createLowerConstantExpressionsPass());
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// Make sure that no unreachable blocks are instruction selected.
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PM.add(createUnreachableBlockEliminationPass());
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// FIXME: ISel
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//PM.add(createPPCSimpleInstructionSelector(TM));
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PM.add(createRegisterAllocator());
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PM.add(createPrologEpilogCodeInserter());
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}
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unsigned PPC64TargetMachine::getModuleMatchQuality(const Module &M) {
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if (M.getEndianness() == Module::BigEndian &&
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M.getPointerSize() == Module::Pointer64)
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return 10; // Direct match
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else if (M.getEndianness() != Module::AnyEndianness ||
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M.getPointerSize() != Module::AnyPointerSize)
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return 0; // Match for some other target
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return getJITMatchQuality()/2;
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}
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@ -31,8 +31,6 @@ public:
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virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM,
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MachineCodeEmitter &MCE);
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virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
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static unsigned getModuleMatchQuality(const Module &M);
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};
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@ -10,8 +10,12 @@
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//
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//===----------------------------------------------------------------------===//
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#include "PowerPCTargetMachine.h"
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#include "PowerPC.h"
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#include "PowerPCTargetMachine.h"
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#include "PPC32TargetMachine.h"
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#include "PPC64TargetMachine.h"
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#include "PPC32JITInfo.h"
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#include "PPC64JITInfo.h"
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#include "llvm/Module.h"
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#include "llvm/PassManager.h"
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#include "llvm/CodeGen/IntrinsicLowering.h"
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@ -20,9 +24,25 @@
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetMachineRegistry.h"
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#include "llvm/Transforms/Scalar.h"
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#include "Support/CommandLine.h"
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#include <iostream>
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using namespace llvm;
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namespace {
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cl::opt<bool>
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AIX("aix",
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cl::desc("Generate AIX/xcoff rather than Darwin/macho"),
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cl::Hidden);
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const std::string PPC32 = "PowerPC/32bit";
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const std::string PPC64 = "PowerPC/64bit";
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// Register the targets
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RegisterTarget<PPC32TargetMachine>
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X("ppc32", " PowerPC 32bit (experimental)");
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RegisterTarget<PPC64TargetMachine>
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Y("ppc64", " PowerPC 64bit (unimplemented)");
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}
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PowerPCTargetMachine::PowerPCTargetMachine(const std::string &name,
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IntrinsicLowering *IL,
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const TargetData &TD,
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@ -38,8 +58,74 @@ unsigned PowerPCTargetMachine::getJITMatchQuality() {
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#endif
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}
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/// addPassesToEmitAssembly - Add passes to the specified pass manager
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/// to implement a static compiler for this target.
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///
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bool PowerPCTargetMachine::addPassesToEmitAssembly(PassManager &PM,
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std::ostream &Out) {
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bool LP64 = (0 != dynamic_cast<PPC64TargetMachine *>(this));
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// FIXME: Implement efficient support for garbage collection intrinsics.
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PM.add(createLowerGCPass());
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// FIXME: Implement the invoke/unwind instructions!
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PM.add(createLowerInvokePass());
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// FIXME: Implement the switch instruction in the instruction selector!
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PM.add(createLowerSwitchPass());
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PM.add(createLowerConstantExpressionsPass());
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// Make sure that no unreachable blocks are instruction selected.
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PM.add(createUnreachableBlockEliminationPass());
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if (LP64)
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PM.add(createPPC32ISelSimple(*this));
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else
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PM.add(createPPC32ISelSimple(*this));
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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PM.add(createRegisterAllocator());
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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// I want a PowerPC specific prolog/epilog code inserter so I can put the
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// fills/spills in the right spots.
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PM.add(createPowerPCPEI());
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// Must run branch selection immediately preceding the printer
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PM.add(createPPCBranchSelectionPass());
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if (AIX)
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PM.add(createPPC32AsmPrinter(Out, *this));
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else
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PM.add(createPPC32AsmPrinter(Out, *this));
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PM.add(createMachineCodeDeleter());
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return false;
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}
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void PowerPCJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
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assert(0 && "Cannot execute PowerPCJITInfo::addPassesToJITCompile()");
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// FIXME: Implement efficient support for garbage collection intrinsics.
|
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PM.add(createLowerGCPass());
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// FIXME: Implement the invoke/unwind instructions!
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PM.add(createLowerInvokePass());
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|
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// FIXME: Implement the switch instruction in the instruction selector!
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PM.add(createLowerSwitchPass());
|
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|
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PM.add(createLowerConstantExpressionsPass());
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// Make sure that no unreachable blocks are instruction selected.
|
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PM.add(createUnreachableBlockEliminationPass());
|
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PM.add(createPPC32ISelSimple(TM));
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PM.add(createRegisterAllocator());
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PM.add(createPrologEpilogCodeInserter());
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}
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void PowerPCJITInfo::replaceMachineCodeForFunction(void *Old, void *New) {
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@ -51,3 +137,42 @@ void *PowerPCJITInfo::getJITStubForFunction(Function *F,
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assert(0 && "Cannot execute PowerPCJITInfo::getJITStubForFunction()");
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return 0;
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}
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|
||||
/// PowerPCTargetMachine ctor - Create an ILP32 architecture model
|
||||
///
|
||||
PPC32TargetMachine::PPC32TargetMachine(const Module &M,
|
||||
IntrinsicLowering *IL)
|
||||
: PowerPCTargetMachine(PPC32, IL,
|
||||
TargetData(PPC32,false,4,4,4,4,4,4,2,1,4),
|
||||
TargetFrameInfo(TargetFrameInfo::StackGrowsDown,16,0),
|
||||
PPC32JITInfo(*this)) {}
|
||||
|
||||
/// PPC64TargetMachine ctor - Create a LP64 architecture model
|
||||
///
|
||||
PPC64TargetMachine::PPC64TargetMachine(const Module &M, IntrinsicLowering *IL)
|
||||
: PowerPCTargetMachine(PPC64, IL,
|
||||
TargetData(PPC64,false,8,4,4,4,4,4,2,1,4),
|
||||
TargetFrameInfo(TargetFrameInfo::StackGrowsDown,16,0),
|
||||
PPC64JITInfo(*this)) {}
|
||||
|
||||
unsigned PPC32TargetMachine::getModuleMatchQuality(const Module &M) {
|
||||
if (M.getEndianness() == Module::BigEndian &&
|
||||
M.getPointerSize() == Module::Pointer32)
|
||||
return 10; // Direct match
|
||||
else if (M.getEndianness() != Module::AnyEndianness ||
|
||||
M.getPointerSize() != Module::AnyPointerSize)
|
||||
return 0; // Match for some other target
|
||||
|
||||
return getJITMatchQuality()/2;
|
||||
}
|
||||
|
||||
unsigned PPC64TargetMachine::getModuleMatchQuality(const Module &M) {
|
||||
if (M.getEndianness() == Module::BigEndian &&
|
||||
M.getPointerSize() == Module::Pointer64)
|
||||
return 10; // Direct match
|
||||
else if (M.getEndianness() != Module::AnyEndianness ||
|
||||
M.getPointerSize() != Module::AnyPointerSize)
|
||||
return 0; // Match for some other target
|
||||
|
||||
return getJITMatchQuality()/2;
|
||||
}
|
||||
|
@ -38,14 +38,7 @@ public:
|
||||
virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM,
|
||||
MachineCodeEmitter &MCE);
|
||||
|
||||
virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
|
||||
|
||||
static unsigned getModuleMatchQuality(const Module &M);
|
||||
|
||||
// Two shared sets between the instruction selector and the printer allow for
|
||||
// correct linkage on Darwin
|
||||
std::set<GlobalValue*> CalledFunctions;
|
||||
std::set<GlobalValue*> AddressTaken;
|
||||
};
|
||||
|
||||
} // end namespace llvm
|
||||
|
@ -46,6 +46,13 @@ public:
|
||||
}
|
||||
|
||||
static unsigned getJITMatchQuality();
|
||||
|
||||
virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
|
||||
|
||||
// Two shared sets between the instruction selector and the printer allow for
|
||||
// correct linkage on Darwin
|
||||
std::set<GlobalValue*> CalledFunctions;
|
||||
std::set<GlobalValue*> AddressTaken;
|
||||
};
|
||||
|
||||
} // end namespace llvm
|
||||
|
Loading…
Reference in New Issue
Block a user