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Remove bunch of gcc 4.3-related warnings from Target

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47369 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov 2008-02-20 11:22:39 +00:00
parent 4c71dfe356
commit 7c1c261272
13 changed files with 31 additions and 24 deletions
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5
lib/Target/ARM/ARMCodeEmitter.cpp
View File

@ -475,8 +475,8 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
}
}
// set the field related to shift operations (except rrx).
if(ARM_AM::getSORegShOp(MO2.getImm()) != ARM_AM::rrx)
if(IsShiftByRegister) {
if (ARM_AM::getSORegShOp(MO2.getImm()) != ARM_AM::rrx) {
if (IsShiftByRegister) {
// set the value of bit[11:8] (register Rs).
assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
op = ARMRegisterInfo::getRegisterNumbering(MO1.getReg());
@ -487,6 +487,7 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
op = ARM_AM::getSORegOffset(MO2.getImm());
Value |= op << 7;
}
}
break;
}
default: assert(false && "Unknown operand type!");

8
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -1551,7 +1551,7 @@ static bool isLegalAddressImmediate(int64_t V, MVT::ValueType VT,
if ((V & (Scale - 1)) != 0)
return false;
V /= Scale;
return V == V & ((1LL << 5) - 1);
return V == (V & ((1LL << 5) - 1));
}
if (V < 0)
@ -1562,10 +1562,10 @@ static bool isLegalAddressImmediate(int64_t V, MVT::ValueType VT,
case MVT::i8:
case MVT::i32:
// +- imm12
return V == V & ((1LL << 12) - 1);
return V == (V & ((1LL << 12) - 1));
case MVT::i16:
// +- imm8
return V == V & ((1LL << 8) - 1);
return V == (V & ((1LL << 8) - 1));
case MVT::f32:
case MVT::f64:
if (!Subtarget->hasVFP2())
@ -1573,7 +1573,7 @@ static bool isLegalAddressImmediate(int64_t V, MVT::ValueType VT,
if ((V & 3) != 0)
return false;
V >>= 2;
return V == V & ((1LL << 8) - 1);
return V == (V & ((1LL << 8) - 1));
}
}

3
lib/Target/ARM/ARMRegisterInfo.cpp
View File

@ -1328,7 +1328,7 @@ void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
if (AFI->getGPRCalleeSavedArea2Size() ||
AFI->getDPRCalleeSavedAreaSize() ||
AFI->getDPRCalleeSavedAreaOffset()||
hasFP(MF))
hasFP(MF)) {
if (NumBytes)
BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr)
.addImm(NumBytes)
@ -1336,6 +1336,7 @@ void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
else
BuildMI(MBB, MBBI, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr)
.addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
}
} else if (NumBytes) {
emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, false, TII, *this);
}

4
lib/Target/Alpha/AlphaRegisterInfo.cpp
View File

@ -272,8 +272,8 @@ void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
MachineBasicBlock::iterator MBBI = prior(MBB.end());
assert(MBBI->getOpcode() == Alpha::RETDAG ||
MBBI->getOpcode() == Alpha::RETDAGp
assert((MBBI->getOpcode() == Alpha::RETDAG ||
MBBI->getOpcode() == Alpha::RETDAGp)
&& "Can only insert epilog into returning blocks");
bool FP = hasFP(MF);

2
lib/Target/CBackend/CBackend.cpp
View File

@ -2912,7 +2912,7 @@ void CWriter::printIndexingExpression(Value *Ptr, gep_type_iterator I,
HasImplicitAddress = false; // HIA is only true if we haven't addressed yet
}
assert(!HasImplicitAddress || (CI && CI->isNullValue()) &&
assert((!HasImplicitAddress || (CI && CI->isNullValue())) &&
"Can only have implicit address with direct accessing");
if (HasImplicitAddress) {

2
lib/Target/IA64/IA64RegisterInfo.h
View File

@ -17,8 +17,6 @@
#include "llvm/Target/TargetRegisterInfo.h"
#include "IA64GenRegisterInfo.h.inc"
namespace llvm { class llvm::Type; }
namespace llvm {
class TargetInstrInfo;

2
lib/Target/MSIL/MSILWriter.cpp
View File

@ -202,7 +202,7 @@ void MSILWriter::printModuleStartup() {
}
bool RetVoid = (F->getReturnType()->getTypeID() == Type::VoidTyID);
if (BadSig || !F->getReturnType()->isInteger() && !RetVoid) {
if (BadSig || (!F->getReturnType()->isInteger() && !RetVoid)) {
Out << "\tldc.i4.0\n";
} else {
Out << "\tcall\t" << getTypeName(F->getReturnType()) <<

4
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -935,7 +935,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
if (LD->getValueType(0) != MVT::i64) {
// Handle PPC32 integer and normal FP loads.
assert(!isSExt || LoadedVT == MVT::i16 && "Invalid sext update load");
assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
switch (LoadedVT) {
default: assert(0 && "Invalid PPC load type!");
case MVT::f64: Opcode = PPC::LFDU; break;
@ -947,7 +947,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
}
} else {
assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
assert(!isSExt || LoadedVT == MVT::i16 && "Invalid sext update load");
assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
switch (LoadedVT) {
default: assert(0 && "Invalid PPC load type!");
case MVT::i64: Opcode = PPC::LDU; break;

3
lib/Target/PowerPC/PPCTargetMachine.cpp
View File

@ -92,11 +92,12 @@ PPCTargetMachine::PPCTargetMachine(const Module &M, const std::string &FS,
FrameInfo(*this, is64Bit), JITInfo(*this, is64Bit), TLInfo(*this),
InstrItins(Subtarget.getInstrItineraryData()), MachOWriterInfo(*this) {
if (getRelocationModel() == Reloc::Default)
if (getRelocationModel() == Reloc::Default) {
if (Subtarget.isDarwin())
setRelocationModel(Reloc::DynamicNoPIC);
else
setRelocationModel(Reloc::Static);
}
}
/// Override this for PowerPC. Tail merging happily breaks up instruction issue

8
lib/Target/X86/X86ISelLowering.cpp
View File

@ -1029,12 +1029,13 @@ bool X86TargetLowering::IsCalleePop(SDOperand Op) {
CCAssignFn *X86TargetLowering::CCAssignFnForNode(SDOperand Op) const {
unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
if (Subtarget->is64Bit())
if (Subtarget->is64Bit()) {
if (CC == CallingConv::Fast && PerformTailCallOpt)
return CC_X86_64_TailCall;
else
return CC_X86_64_C;
}
if (CC == CallingConv::X86_FastCall)
return CC_X86_32_FastCall;
else if (CC == CallingConv::Fast && PerformTailCallOpt)
@ -3358,11 +3359,12 @@ SDOperand RewriteAsNarrowerShuffle(SDOperand V1, SDOperand V2,
default: assert(false && "Unexpected!");
}
if (NewWidth == 2)
if (NewWidth == 2) {
if (MVT::isInteger(VT))
NewVT = MVT::v2i64;
else
NewVT = MVT::v2f64;
}
unsigned Scale = NumElems / NewWidth;
SmallVector<SDOperand, 8> MaskVec;
for (unsigned i = 0; i < NumElems; i += Scale) {

3
lib/Target/X86/X86IntelAsmPrinter.cpp
View File

@ -221,13 +221,14 @@ void X86IntelAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
} else {
int DispVal = DispSpec.getImm();
if (DispVal || (!BaseReg.getReg() && !IndexReg.getReg())) {
if (NeedPlus)
if (NeedPlus) {
if (DispVal > 0)
O << " + ";
else {
O << " - ";
DispVal = -DispVal;
}
}
O << DispVal;
}
}

3
lib/Target/X86/X86Subtarget.cpp
View File

@ -36,7 +36,7 @@ bool X86Subtarget::GVRequiresExtraLoad(const GlobalValue* GV,
bool isDirectCall) const
{
// FIXME: PIC
if (TM.getRelocationModel() != Reloc::Static)
if (TM.getRelocationModel() != Reloc::Static) {
if (isTargetDarwin()) {
return (!isDirectCall &&
(GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
@ -48,6 +48,7 @@ bool X86Subtarget::GVRequiresExtraLoad(const GlobalValue* GV,
} else if (isTargetCygMing() || isTargetWindows()) {
return (GV->hasDLLImportLinkage());
}
}
return false;
}

8
lib/Target/X86/X86TargetMachine.cpp
View File

@ -119,11 +119,12 @@ X86TargetMachine::X86TargetMachine(const Module &M, const std::string &FS,
Subtarget.getStackAlignment(), Subtarget.is64Bit() ? -8 : -4),
InstrInfo(*this), JITInfo(*this), TLInfo(*this) {
DefRelocModel = getRelocationModel();
if (getRelocationModel() == Reloc::Default)
if (getRelocationModel() == Reloc::Default) {
if (Subtarget.isTargetDarwin() || Subtarget.isTargetCygMing())
setRelocationModel(Reloc::DynamicNoPIC);
else
setRelocationModel(Reloc::Static);
}
if (Subtarget.is64Bit()) {
// No DynamicNoPIC support under X86-64.
if (getRelocationModel() == Reloc::DynamicNoPIC)
@ -135,16 +136,17 @@ X86TargetMachine::X86TargetMachine(const Module &M, const std::string &FS,
if (Subtarget.isTargetCygMing())
Subtarget.setPICStyle(PICStyle::WinPIC);
else if (Subtarget.isTargetDarwin())
else if (Subtarget.isTargetDarwin()) {
if (Subtarget.is64Bit())
Subtarget.setPICStyle(PICStyle::RIPRel);
else
Subtarget.setPICStyle(PICStyle::Stub);
else if (Subtarget.isTargetELF())
} else if (Subtarget.isTargetELF()) {
if (Subtarget.is64Bit())
Subtarget.setPICStyle(PICStyle::RIPRel);
else
Subtarget.setPICStyle(PICStyle::GOT);
}
}
//===----------------------------------------------------------------------===//