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Thumb-2 only support [base_reg + offset_reg] addressing, not [base_reg - offset_reg].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75789 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -613,23 +613,21 @@ bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue Op, SDValue N,
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bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue Op, SDValue N,
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SDValue &Base, SDValue &OffImm) {
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if (N.getOpcode() == ISD::ADD) {
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if ((N.getOpcode() == ISD::ADD) || (N.getOpcode() == ISD::SUB)) {
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if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
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int RHSC = (int)RHS->getZExtValue();
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if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
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int RHSC = (int)RHS->getSExtValue();
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if (N.getOpcode() == ISD::SUB)
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RHSC = -RHSC;
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if ((RHSC >= -255) && (RHSC <= 255)) { // sign + 8 bits.
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Base = N.getOperand(0);
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OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
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return true;
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}
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}
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} else if (N.getOpcode() == ISD::SUB) {
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if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
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int RHSC = (int)RHS->getZExtValue();
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if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
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Base = N.getOperand(0);
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OffImm = CurDAG->getTargetConstant(-RHSC, MVT::i32);
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return true;
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}
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} else if (N.getOpcode() == ISD::SUB) {
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Base = N;
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OffImm = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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}
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@ -700,6 +698,10 @@ bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue Op, SDValue N,
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return true;
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}
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// Thumb2 does not support (R - R) or (R - (R << [1,2,3])).
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if (N.getOpcode() != ISD::ADD)
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return false;
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// Look for (R + R) or (R + (R << [1,2,3])).
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unsigned ShAmt = 0;
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Base = N.getOperand(0);
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@ -727,9 +729,10 @@ bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue Op, SDValue N,
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ShOpcVal = ARM_AM::no_shift;
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}
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} else if (SelectT2AddrModeImm12(Op, N, Base, ShImm) ||
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SelectT2AddrModeImm8 (Op, N, Base, ShImm))
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SelectT2AddrModeImm8 (Op, N, Base, ShImm)) {
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// Don't match if it's possible to match to one of the r +/- imm cases.
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return false;
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}
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ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
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