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Eliminate big-endian subtargets of Mos6502

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They were copied from SPARC V8 and V9.
This commit is contained in:
Damián Silvani
2015-08-03 17:03:45 -03:00
parent 36ee8fe697
commit 964a041a08
13 changed files with 31 additions and 177 deletions
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4
lib/Target/Mos6502/MCTargetDesc/Mos6502AsmBackend.cpp
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@@ -106,8 +106,8 @@ namespace {
public:
Mos6502AsmBackend(const Target &T)
: MCAsmBackend(), TheTarget(T),
IsLittleEndian(StringRef(TheTarget.getName()) == "mos6502el"),
Is64Bit(StringRef(TheTarget.getName()) == "mos6502v9") {}
IsLittleEndian(true),
Is64Bit(false) {}
unsigned getNumFixupKinds() const override {
return Mos6502::NumTargetFixupKinds;

4
lib/Target/Mos6502/MCTargetDesc/Mos6502MCAsmInfo.cpp
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@@ -21,8 +21,8 @@ using namespace llvm;
void Mos6502ELFMCAsmInfo::anchor() {}
Mos6502ELFMCAsmInfo::Mos6502ELFMCAsmInfo(const Triple &TheTriple) {
bool isV9 = (TheTriple.getArch() == Triple::mos6502v9);
IsLittleEndian = (TheTriple.getArch() == Triple::mos6502el);
bool isV9 = false;
IsLittleEndian = true;
if (isV9) {
PointerSize = CalleeSaveStackSlotSize = 8;

43
lib/Target/Mos6502/MCTargetDesc/Mos6502MCTargetDesc.cpp
View File

@@ -42,15 +42,6 @@ static MCAsmInfo *createMos6502MCAsmInfo(const MCRegisterInfo &MRI,
return MAI;
}
static MCAsmInfo *createMos6502V9MCAsmInfo(const MCRegisterInfo &MRI,
const Triple &TT) {
MCAsmInfo *MAI = new Mos6502ELFMCAsmInfo(TT);
unsigned Reg = MRI.getDwarfRegNum(SP::O6, true);
MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 2047);
MAI->addInitialFrameState(Inst);
return MAI;
}
static MCInstrInfo *createMos6502MCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo();
InitMos6502MCInstrInfo(X);
@@ -66,7 +57,7 @@ static MCRegisterInfo *createMos6502MCRegisterInfo(const Triple &TT) {
static MCSubtargetInfo *
createMos6502MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
if (CPU.empty())
CPU = (TT.getArch() == Triple::mos6502v9) ? "v9" : "v8";
CPU = "v8";
return createMos6502MCSubtargetInfoImpl(TT, CPU, FS);
}
@@ -99,28 +90,6 @@ static MCCodeGenInfo *createMos6502MCCodeGenInfo(const Triple &TT,
return X;
}
static MCCodeGenInfo *createMos6502V9MCCodeGenInfo(const Triple &TT,
Reloc::Model RM,
CodeModel::Model CM,
CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo();
// The default 64-bit code model is abs44/pic32 and the default 64-bit
// code model for JIT is abs64.
switch (CM) {
default: break;
case CodeModel::Default:
CM = RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium;
break;
case CodeModel::JITDefault:
CM = CodeModel::Large;
break;
}
X->initMCCodeGenInfo(RM, CM, OL);
return X;
}
static MCTargetStreamer *
createObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
return new Mos6502TargetELFStreamer(S);
@@ -143,11 +112,9 @@ static MCInstPrinter *createMos6502MCInstPrinter(const Triple &T,
extern "C" void LLVMInitializeMos6502TargetMC() {
// Register the MC asm info.
RegisterMCAsmInfoFn X(TheMos6502Target, createMos6502MCAsmInfo);
RegisterMCAsmInfoFn Y(TheMos6502V9Target, createMos6502V9MCAsmInfo);
RegisterMCAsmInfoFn Z(TheMos6502elTarget, createMos6502MCAsmInfo);
RegisterMCAsmInfoFn Z(TheMos6502Target, createMos6502MCAsmInfo);
for (Target *T : {&TheMos6502Target, &TheMos6502V9Target, &TheMos6502elTarget}) {
for (Target *T : {&TheMos6502Target}) {
// Register the MC instruction info.
TargetRegistry::RegisterMCInstrInfo(*T, createMos6502MCInstrInfo);
@@ -177,8 +144,4 @@ extern "C" void LLVMInitializeMos6502TargetMC() {
// Register the MC codegen info.
TargetRegistry::RegisterMCCodeGenInfo(TheMos6502Target,
createMos6502MCCodeGenInfo);
TargetRegistry::RegisterMCCodeGenInfo(TheMos6502V9Target,
createMos6502V9MCCodeGenInfo);
TargetRegistry::RegisterMCCodeGenInfo(TheMos6502elTarget,
createMos6502MCCodeGenInfo);
}

2
lib/Target/Mos6502/MCTargetDesc/Mos6502MCTargetDesc.h
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@@ -31,8 +31,6 @@ class raw_pwrite_stream;
class raw_ostream;
extern Target TheMos6502Target;
extern Target TheMos6502V9Target;
extern Target TheMos6502elTarget;
MCCodeEmitter *createMos6502MCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,