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[mips] Fix floating point branch, comparison, and conditional move instructions

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to have register FCC0 (the first floating point condition code register) in
their Uses/Defs list.

No intended functionality change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187233 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2013-07-26 19:01:56 +00:00
parent d6a7ea2736
commit 9955cb931b
2 changed files with 4 additions and 4 deletions
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4
lib/Target/Mips/MipsCondMov.td
View File

@ -37,7 +37,7 @@ class CMov_F_I_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
InstSE<(outs RC:$rd), (ins RC:$rs, RC:$F),
!strconcat(opstr, "\t$rd, $rs, $$fcc0"),
[(set RC:$rd, (OpNode RC:$rs, RC:$F))], Itin, FrmFR> {
let Uses = [FCR31];
let Uses = [FCC0];
let Constraints = "$F = $rd";
}
@ -47,7 +47,7 @@ class CMov_F_F_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
InstSE<(outs RC:$fd), (ins RC:$fs, RC:$F),
!strconcat(opstr, "\t$fd, $fs, $$fcc0"),
[(set RC:$fd, (OpNode RC:$fs, RC:$F))], Itin, FrmFR> {
let Uses = [FCR31];
let Uses = [FCC0];
let Constraints = "$F = $fd";
}

4
lib/Target/Mips/MipsInstrFPU.td
View File

@ -194,7 +194,7 @@ class BC1F_FT<string opstr, InstrItinClass Itin,
let isTerminator = 1;
let hasDelaySlot = 1;
let Defs = [AT];
let Uses = [FCR31];
let Uses = [FCC0];
}
class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin,
@ -202,7 +202,7 @@ class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin,
InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond),
!strconcat("c.$cond.", typestr, "\t$fs, $ft"),
[(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR> {
let Defs = [FCR31];
let Defs = [FCC0];
let isCodeGenOnly = 1;
}