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Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138575 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2539,8 +2539,8 @@ static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
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Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
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CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));
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Inst.addOperand(MCOperand::CreateReg(ARM::SP));
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CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));
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Inst.addOperand(MCOperand::CreateReg(ARM::SP));
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} else if (Inst.getOpcode() == ARM::tADDspr) {
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unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
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@ -28,6 +28,29 @@
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0xd1 0x18
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0x42 0x44
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#------------------------------------------------------------------------------
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# ADD (SP plus immediate)
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#------------------------------------------------------------------------------
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# CHECK: add sp, #508
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# CHECK: add sp, #4
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# CHECK: add r2, sp, #8
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# CHECK: add r2, sp, #1020
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0x7f 0xb0
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0x01 0xb0
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0x02 0xaa
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0xff 0xaa
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#------------------------------------------------------------------------------
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# ADD (SP plus register)
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#------------------------------------------------------------------------------
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# CHECK: add sp, r3
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# CHECK: add r2, sp, r2
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0x9d 0x44
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0x6a 0x44
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#------------------------------------------------------------------------------
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# ASR (immediate)
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#------------------------------------------------------------------------------
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@ -442,6 +465,14 @@
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0xd1 0x1a
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#------------------------------------------------------------------------------
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# SUB (SP minus immediate)
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#------------------------------------------------------------------------------
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# CHECK: sub sp, #12
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# CHECK: sub sp, #508
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0x83 0xb0
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0xff 0xb0
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#------------------------------------------------------------------------------
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# SVC
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