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Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138575 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
2011-08-25 18:30:18 +00:00
parent cf847bfa6f
commit 99906830e8
2 changed files with 32 additions and 1 deletions
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2
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -2539,8 +2539,8 @@ static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)); CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));
Inst.addOperand(MCOperand::CreateReg(ARM::SP));
CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)); CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));
Inst.addOperand(MCOperand::CreateReg(ARM::SP));
} else if (Inst.getOpcode() == ARM::tADDspr) { } else if (Inst.getOpcode() == ARM::tADDspr) {
unsigned Rm = fieldFromInstruction16(Insn, 3, 4); unsigned Rm = fieldFromInstruction16(Insn, 3, 4);

31
test/MC/Disassembler/ARM/thumb1.txt
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@ -28,6 +28,29 @@
0xd1 0x18 0xd1 0x18
0x42 0x44 0x42 0x44
#------------------------------------------------------------------------------
# ADD (SP plus immediate)
#------------------------------------------------------------------------------
# CHECK: add sp, #508
# CHECK: add sp, #4
# CHECK: add r2, sp, #8
# CHECK: add r2, sp, #1020
0x7f 0xb0
0x01 0xb0
0x02 0xaa
0xff 0xaa
#------------------------------------------------------------------------------
# ADD (SP plus register)
#------------------------------------------------------------------------------
# CHECK: add sp, r3
# CHECK: add r2, sp, r2
0x9d 0x44
0x6a 0x44
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# ASR (immediate) # ASR (immediate)
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
@ -442,6 +465,14 @@
0xd1 0x1a 0xd1 0x1a
#------------------------------------------------------------------------------
# SUB (SP minus immediate)
#------------------------------------------------------------------------------
# CHECK: sub sp, #12
# CHECK: sub sp, #508
0x83 0xb0
0xff 0xb0
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# SVC # SVC