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Add vector versions of some existing scalar transforms to aid codegen in matching psign & pblend operations to the IR produced by clang/gcc for their C idioms.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122105 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2010-12-17 23:12:19 +00:00
parent 976ef86689
commit 9a3dc55202
3 changed files with 46 additions and 0 deletions
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7
lib/Analysis/ValueTracking.cpp
View File

@ -678,6 +678,13 @@ unsigned llvm::ComputeNumSignBits(Value *V, const TargetData *TD,
Tmp += C->getZExtValue();
if (Tmp > TyBits) Tmp = TyBits;
}
// vector ashr X, <C, C, C, C> -> adds C sign bits
if (ConstantVector *C = dyn_cast<ConstantVector>(U->getOperand(1))) {
if (ConstantInt *CI = dyn_cast_or_null<ConstantInt>(C->getSplatValue())) {
Tmp += CI->getZExtValue();
if (Tmp > TyBits) Tmp = TyBits;
}
}
return Tmp;
case Instruction::Shl:
if (ConstantInt *C = dyn_cast<ConstantInt>(U->getOperand(1))) {

17
lib/Transforms/InstCombine/InstCombineCasts.cpp
View File

@ -1020,6 +1020,23 @@ Instruction *InstCombiner::visitSExt(SExtInst &CI) {
}
}
// vector (x <s 0) ? -1 : 0 -> ashr x, 31 -> all ones if signed
if (const VectorType *VTy = dyn_cast<VectorType>(DestTy)) {
ICmpInst::Predicate Pred; Value *CmpLHS;
if (match(Src, m_ICmp(Pred, m_Value(CmpLHS), m_Zero()))) {
if (Pred == ICmpInst::ICMP_SLT && CmpLHS->getType() == DestTy) {
const Type *EltTy = VTy->getElementType();
// splat the shift constant to a cosntant vector
Constant *Sh = ConstantInt::get(EltTy, EltTy->getScalarSizeInBits()-1);
std::vector<Constant *> Elts(VTy->getNumElements(), Sh);
Constant *VSh = ConstantVector::get(Elts);
Value *In = Builder->CreateAShr(CmpLHS, VSh, CmpLHS->getName()+".lobit");
return ReplaceInstUsesWith(CI, In);
}
}
}
// If the input is a shl/ashr pair of a same constant, then this is a sign
// extension from a smaller value. If we could trust arbitrary bitwidth

22
test/Transforms/InstCombine/vec_sext.ll Normal file
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@ -0,0 +1,22 @@
; RUN: opt < %s -instcombine -S | FileCheck %s
define <4 x i32> @psignd_3(<4 x i32> %a, <4 x i32> %b) nounwind ssp {
entry:
%cmp = icmp slt <4 x i32> %b, zeroinitializer
%sext = sext <4 x i1> %cmp to <4 x i32>
%sub = sub nsw <4 x i32> zeroinitializer, %a
%0 = icmp slt <4 x i32> %sext, zeroinitializer
%sext3 = sext <4 x i1> %0 to <4 x i32>
%1 = xor <4 x i32> %sext3, <i32 -1, i32 -1, i32 -1, i32 -1>
%2 = and <4 x i32> %a, %1
%3 = and <4 x i32> %sext3, %sub
%cond = or <4 x i32> %2, %3
ret <4 x i32> %cond
; CHECK: ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
; CHECK: sub nsw <4 x i32> zeroinitializer, %a
; CHECK: xor <4 x i32> %b.lobit, <i32 -1, i32 -1, i32 -1, i32 -1>
; CHECK: and <4 x i32> %a, %0
; CHECK: and <4 x i32> %b.lobit, %sub
; CHECK: or <4 x i32> %1, %2
}