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https://github.com/c64scene-ar/llvm-6502.git
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misched: Target-independent support for load/store clustering.
This infrastructure is generally useful for any target that wants to strongly prefer two instructions to be adjacent after scheduling. A following checkin will add target-specific hooks with unit tests. Then this feature will be enabled by default with misched. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167742 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick
parent
0a46bf13a3
commit
9b5caaa9c4
@ -202,6 +202,10 @@ protected:
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RegisterClassInfo *RegClassInfo;
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MachineSchedStrategy *SchedImpl;
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/// Topo - A topological ordering for SUnits which permits fast IsReachable
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/// and similar queries.
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ScheduleDAGTopologicalSort Topo;
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/// Ordered list of DAG postprocessing steps.
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std::vector<ScheduleDAGMutation*> Mutations;
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@ -226,6 +230,10 @@ protected:
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IntervalPressure BotPressure;
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RegPressureTracker BotRPTracker;
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/// Record the next node in a scheduled cluster.
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const SUnit *NextClusterPred;
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const SUnit *NextClusterSucc;
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#ifndef NDEBUG
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/// The number of instructions scheduled so far. Used to cut off the
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/// scheduler at the point determined by misched-cutoff.
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@ -236,24 +244,35 @@ public:
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ScheduleDAGMI(MachineSchedContext *C, MachineSchedStrategy *S):
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ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, /*IsPostRA=*/false, C->LIS),
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AA(C->AA), RegClassInfo(C->RegClassInfo), SchedImpl(S),
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RPTracker(RegPressure), CurrentTop(), TopRPTracker(TopPressure),
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CurrentBottom(), BotRPTracker(BotPressure) {
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Topo(SUnits, &ExitSU), RPTracker(RegPressure), CurrentTop(),
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TopRPTracker(TopPressure), CurrentBottom(), BotRPTracker(BotPressure),
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NextClusterPred(NULL), NextClusterSucc(NULL) {
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#ifndef NDEBUG
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NumInstrsScheduled = 0;
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#endif
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}
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virtual ~ScheduleDAGMI() {
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DeleteContainerPointers(Mutations);
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delete SchedImpl;
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}
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/// Add a postprocessing step to the DAG builder.
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/// Mutations are applied in the order that they are added after normal DAG
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/// building and before MachineSchedStrategy initialization.
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///
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/// ScheduleDAGMI takes ownership of the Mutation object.
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void addMutation(ScheduleDAGMutation *Mutation) {
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Mutations.push_back(Mutation);
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}
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/// \brief Add a DAG edge to the given SU with the given predecessor
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/// dependence data.
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///
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/// \returns true if the edge may be added without creating a cycle OR if an
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/// equivalent edge already existed (false indicates failure).
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bool addEdge(SUnit *SuccSU, const SDep &PredDep);
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MachineBasicBlock::iterator top() const { return CurrentTop; }
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MachineBasicBlock::iterator bottom() const { return CurrentBottom; }
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@ -285,6 +304,10 @@ public:
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return RegionCriticalPSets;
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}
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const SUnit *getNextClusterPred() const { return NextClusterPred; }
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const SUnit *getNextClusterSucc() const { return NextClusterSucc; }
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protected:
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// Top-Level entry points for the schedule() driver...
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@ -621,6 +621,19 @@ public:
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return false;
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}
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/// \brief Get the base register and byte offset of a load/store instr.
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virtual bool getLdStBaseRegImmOfs(MachineInstr *LdSt,
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unsigned &BaseReg, unsigned &Offset,
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const TargetRegisterInfo *TRI) const {
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return false;
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}
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virtual bool shouldScheduleLoadsNear(MachineInstr *FirstLdSt,
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MachineInstr *SecondLdSt,
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unsigned NumLoads) const {
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return false;
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}
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/// ReverseBranchCondition - Reverses the branch condition of the specified
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/// condition list, returning false on success and true if it cannot be
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/// reversed.
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@ -58,6 +58,10 @@ static cl::opt<unsigned> ILPWindow("ilp-window", cl::Hidden,
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"before attempting to balance ILP"),
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cl::init(10U));
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// Experimental heuristics
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static cl::opt<bool> EnableLoadCluster("misched-cluster", cl::Hidden,
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cl::desc("Enable load clustering."));
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//===----------------------------------------------------------------------===//
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// Machine Instruction Scheduling Pass and Registry
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//===----------------------------------------------------------------------===//
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@ -303,6 +307,17 @@ void ReadyQueue::dump() {
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// preservation.
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//===----------------------------------------------------------------------===//
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bool ScheduleDAGMI::addEdge(SUnit *SuccSU, const SDep &PredDep) {
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// Do not use WillCreateCycle, it assumes SD scheduling.
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// If Pred is reachable from Succ, then the edge creates a cycle.
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if (Topo.IsReachable(PredDep.getSUnit(), SuccSU))
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return false;
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Topo.AddPred(SuccSU, PredDep.getSUnit());
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SuccSU->addPred(PredDep, /*Required=*/!PredDep.isArtificial());
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// Return true regardless of whether a new edge needed to be inserted.
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return true;
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}
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/// ReleaseSucc - Decrement the NumPredsLeft count of a successor. When
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/// NumPredsLeft reaches zero, release the successor node.
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///
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@ -312,6 +327,8 @@ void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) {
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if (SuccEdge->isWeak()) {
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--SuccSU->WeakPredsLeft;
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if (SuccEdge->isCluster())
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NextClusterSucc = SuccSU;
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return;
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}
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#ifndef NDEBUG
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@ -344,6 +361,8 @@ void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) {
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if (PredEdge->isWeak()) {
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--PredSU->WeakSuccsLeft;
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if (PredEdge->isCluster())
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NextClusterPred = PredSU;
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return;
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}
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#ifndef NDEBUG
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@ -482,6 +501,8 @@ updateScheduledPressure(std::vector<unsigned> NewMaxPressure) {
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void ScheduleDAGMI::schedule() {
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buildDAGWithRegPressure();
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Topo.InitDAGTopologicalSorting();
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postprocessDAG();
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DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
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@ -562,6 +583,8 @@ void ScheduleDAGMI::releaseRoots() {
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/// Identify DAG roots and setup scheduler queues.
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void ScheduleDAGMI::initQueues() {
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NextClusterSucc = NULL;
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NextClusterPred = NULL;
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// Initialize the strategy before modifying the DAG.
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SchedImpl->initialize(this);
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@ -664,6 +687,119 @@ void ScheduleDAGMI::dumpSchedule() const {
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}
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#endif
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namespace {
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/// \brief Post-process the DAG to create cluster edges between neighboring
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/// loads.
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class LoadClusterMutation : public ScheduleDAGMutation {
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struct LoadInfo {
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SUnit *SU;
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unsigned BaseReg;
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unsigned Offset;
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LoadInfo(SUnit *su, unsigned reg, unsigned ofs)
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: SU(su), BaseReg(reg), Offset(ofs) {}
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};
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static bool LoadInfoLess(const LoadClusterMutation::LoadInfo &LHS,
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const LoadClusterMutation::LoadInfo &RHS);
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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public:
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LoadClusterMutation(const TargetInstrInfo *tii,
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const TargetRegisterInfo *tri)
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: TII(tii), TRI(tri) {}
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virtual void apply(ScheduleDAGMI *DAG);
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protected:
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void clusterNeighboringLoads(ArrayRef<SUnit*> Loads, ScheduleDAGMI *DAG);
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};
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} // anonymous
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bool LoadClusterMutation::LoadInfoLess(
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const LoadClusterMutation::LoadInfo &LHS,
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const LoadClusterMutation::LoadInfo &RHS) {
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if (LHS.BaseReg != RHS.BaseReg)
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return LHS.BaseReg < RHS.BaseReg;
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return LHS.Offset < RHS.Offset;
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}
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void LoadClusterMutation::clusterNeighboringLoads(ArrayRef<SUnit*> Loads,
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ScheduleDAGMI *DAG) {
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SmallVector<LoadClusterMutation::LoadInfo,32> LoadRecords;
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for (unsigned Idx = 0, End = Loads.size(); Idx != End; ++Idx) {
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SUnit *SU = Loads[Idx];
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unsigned BaseReg;
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unsigned Offset;
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if (TII->getLdStBaseRegImmOfs(SU->getInstr(), BaseReg, Offset, TRI))
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LoadRecords.push_back(LoadInfo(SU, BaseReg, Offset));
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}
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if (LoadRecords.size() < 2)
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return;
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std::sort(LoadRecords.begin(), LoadRecords.end(), LoadInfoLess);
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unsigned ClusterLength = 1;
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for (unsigned Idx = 0, End = LoadRecords.size(); Idx < (End - 1); ++Idx) {
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if (LoadRecords[Idx].BaseReg != LoadRecords[Idx+1].BaseReg) {
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ClusterLength = 1;
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continue;
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}
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SUnit *SUa = LoadRecords[Idx].SU;
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SUnit *SUb = LoadRecords[Idx+1].SU;
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if (TII->shouldScheduleLoadsNear(SUa->getInstr(), SUb->getInstr(),
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ClusterLength)
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&& DAG->addEdge(SUb, SDep(SUa, SDep::Cluster))) {
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DEBUG(dbgs() << "Cluster loads SU(" << SUa->NodeNum << ") - SU("
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<< SUb->NodeNum << ")\n");
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// Copy successor edges from SUa to SUb. Interleaving computation
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// dependent on SUa can prevent load combining due to register reuse.
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// Predecessor edges do not need to be copied from SUb to SUa since nearby
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// loads should have effectively the same inputs.
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for (SUnit::const_succ_iterator
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SI = SUa->Succs.begin(), SE = SUa->Succs.end(); SI != SE; ++SI) {
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if (SI->getSUnit() == SUb)
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continue;
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DEBUG(dbgs() << " Copy Succ SU(" << SI->getSUnit()->NodeNum << ")\n");
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DAG->addEdge(SI->getSUnit(), SDep(SUb, SDep::Artificial));
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}
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++ClusterLength;
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}
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else
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ClusterLength = 1;
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}
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}
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/// \brief Callback from DAG postProcessing to create cluster edges for loads.
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void LoadClusterMutation::apply(ScheduleDAGMI *DAG) {
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// Map DAG NodeNum to store chain ID.
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DenseMap<unsigned, unsigned> StoreChainIDs;
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// Map each store chain to a set of dependent loads.
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SmallVector<SmallVector<SUnit*,4>, 32> StoreChainDependents;
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for (unsigned Idx = 0, End = DAG->SUnits.size(); Idx != End; ++Idx) {
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SUnit *SU = &DAG->SUnits[Idx];
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if (!SU->getInstr()->mayLoad())
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continue;
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unsigned ChainPredID = DAG->SUnits.size();
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for (SUnit::const_pred_iterator
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PI = SU->Preds.begin(), PE = SU->Preds.end(); PI != PE; ++PI) {
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if (PI->isCtrl()) {
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ChainPredID = PI->getSUnit()->NodeNum;
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break;
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}
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}
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// Check if this chain-like pred has been seen
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// before. ChainPredID==MaxNodeID for loads at the top of the schedule.
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unsigned NumChains = StoreChainDependents.size();
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std::pair<DenseMap<unsigned, unsigned>::iterator, bool> Result =
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StoreChainIDs.insert(std::make_pair(ChainPredID, NumChains));
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if (Result.second)
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StoreChainDependents.resize(NumChains + 1);
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StoreChainDependents[Result.first->second].push_back(SU);
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}
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// Iterate over the store chains.
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for (unsigned Idx = 0, End = StoreChainDependents.size(); Idx != End; ++Idx)
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clusterNeighboringLoads(StoreChainDependents[Idx], DAG);
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}
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//===----------------------------------------------------------------------===//
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// ConvergingScheduler - Implementation of the standard MachineSchedStrategy.
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//===----------------------------------------------------------------------===//
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@ -676,9 +812,10 @@ public:
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/// Represent the type of SchedCandidate found within a single queue.
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/// pickNodeBidirectional depends on these listed by decreasing priority.
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enum CandReason {
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NoCand, SingleExcess, SingleCritical, ResourceReduce, ResourceDemand,
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BotHeightReduce, BotPathReduce, TopDepthReduce, TopPathReduce,
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SingleMax, MultiPressure, NextDefUse, NodeOrder};
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NoCand, SingleExcess, SingleCritical, Cluster,
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ResourceReduce, ResourceDemand, BotHeightReduce, BotPathReduce,
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TopDepthReduce, TopPathReduce, SingleMax, MultiPressure, NextDefUse,
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NodeOrder};
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#ifndef NDEBUG
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static const char *getReasonStr(ConvergingScheduler::CandReason Reason);
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@ -1029,6 +1166,8 @@ void ConvergingScheduler::releaseBottomNode(SUnit *SU) {
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for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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I != E; ++I) {
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if (I->isWeak())
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continue;
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unsigned SuccReadyCycle = I->getSUnit()->BotReadyCycle;
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unsigned MinLatency = I->getMinLatency();
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#ifndef NDEBUG
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@ -1424,6 +1563,7 @@ static bool tryLess(unsigned TryVal, unsigned CandVal,
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}
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return false;
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}
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static bool tryGreater(unsigned TryVal, unsigned CandVal,
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ConvergingScheduler::SchedCandidate &TryCand,
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ConvergingScheduler::SchedCandidate &Cand,
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@ -1440,6 +1580,10 @@ static bool tryGreater(unsigned TryVal, unsigned CandVal,
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return false;
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}
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static unsigned getWeakLeft(const SUnit *SU, bool isTop) {
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return (isTop) ? SU->WeakPredsLeft : SU->WeakSuccsLeft;
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}
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/// Apply a set of heursitics to a new candidate. Heuristics are currently
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/// hierarchical. This may be more efficient than a graduated cost model because
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/// we don't need to evaluate all aspects of the model for each node in the
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@ -1482,6 +1626,26 @@ void ConvergingScheduler::tryCandidate(SchedCandidate &Cand,
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if (Cand.Reason == SingleCritical)
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Cand.Reason = MultiPressure;
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// Keep clustered nodes together to encourage downstream peephole
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// optimizations which may reduce resource requirements.
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//
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// This is a best effort to set things up for a post-RA pass. Optimizations
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// like generating loads of multiple registers should ideally be done within
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// the scheduler pass by combining the loads during DAG postprocessing.
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const SUnit *NextClusterSU =
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Zone.isTop() ? DAG->getNextClusterSucc() : DAG->getNextClusterPred();
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if (tryGreater(TryCand.SU == NextClusterSU, Cand.SU == NextClusterSU,
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TryCand, Cand, Cluster))
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return;
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// Currently, weak edges are for clustering, so we hard-code that reason.
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// However, deferring the current TryCand will not change Cand's reason.
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CandReason OrigReason = Cand.Reason;
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if (tryLess(getWeakLeft(TryCand.SU, Zone.isTop()),
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getWeakLeft(Cand.SU, Zone.isTop()),
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TryCand, Cand, Cluster)) {
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Cand.Reason = OrigReason;
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return;
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}
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// Avoid critical resource consumption and balance the schedule.
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TryCand.initResourceDelta(DAG, SchedModel);
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if (tryLess(TryCand.ResDelta.CritResources, Cand.ResDelta.CritResources,
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@ -1528,15 +1692,10 @@ void ConvergingScheduler::tryCandidate(SchedCandidate &Cand,
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// Prefer immediate defs/users of the last scheduled instruction. This is a
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// nice pressure avoidance strategy that also conserves the processor's
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// register renaming resources and keeps the machine code readable.
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if (Zone.NextSUs.count(TryCand.SU) && !Zone.NextSUs.count(Cand.SU)) {
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TryCand.Reason = NextDefUse;
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if (tryGreater(Zone.NextSUs.count(TryCand.SU), Zone.NextSUs.count(Cand.SU),
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TryCand, Cand, NextDefUse))
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return;
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}
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if (!Zone.NextSUs.count(TryCand.SU) && Zone.NextSUs.count(Cand.SU)) {
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if (Cand.Reason > NextDefUse)
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Cand.Reason = NextDefUse;
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return;
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}
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// Fall through to original instruction order.
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if ((Zone.isTop() && TryCand.SU->NodeNum < Cand.SU->NodeNum)
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|| (!Zone.isTop() && TryCand.SU->NodeNum > Cand.SU->NodeNum)) {
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@ -1582,6 +1741,7 @@ const char *ConvergingScheduler::getReasonStr(
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case NoCand: return "NOCAND ";
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case SingleExcess: return "REG-EXCESS";
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case SingleCritical: return "REG-CRIT ";
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case Cluster: return "CLUSTER ";
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case SingleMax: return "REG-MAX ";
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case MultiPressure: return "REG-MULTI ";
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case ResourceReduce: return "RES-REDUCE";
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@ -1822,7 +1982,11 @@ void ConvergingScheduler::schedNode(SUnit *SU, bool IsTopNode) {
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static ScheduleDAGInstrs *createConvergingSched(MachineSchedContext *C) {
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assert((!ForceTopDown || !ForceBottomUp) &&
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"-misched-topdown incompatible with -misched-bottomup");
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return new ScheduleDAGMI(C, new ConvergingScheduler());
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ScheduleDAGMI *DAG = new ScheduleDAGMI(C, new ConvergingScheduler());
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// Register DAG post-processors.
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if (EnableLoadCluster)
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DAG->addMutation(new LoadClusterMutation(DAG->TII, DAG->TRI));
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return DAG;
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}
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static MachineSchedRegistry
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ConvergingSchedRegistry("converge", "Standard converging scheduler.",
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@ -1373,6 +1373,9 @@ bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
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/// only return true if the base pointers are the same and the only differences
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/// between the two addresses is the offset. It also returns the offsets by
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/// reference.
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///
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/// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
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/// is permanently disabled.
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bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
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int64_t &Offset1,
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int64_t &Offset2) const {
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@ -1447,6 +1450,9 @@ bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
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/// from the common base address. It returns true if it decides it's desirable
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/// to schedule the two loads together. "NumLoads" is the number of loads that
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/// have already been scheduled after Load1.
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///
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/// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
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/// is permanently disabled.
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bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
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int64_t Offset1, int64_t Offset2,
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unsigned NumLoads) const {
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