Update tblgen command guide. Remove unused tblgen InstrEnumEmitter files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151513 91177308-0d34-0410-b5e6-96231b3b80d8

docs/CommandGuide/tblgen.pod

@@ -41,6 +41,10 @@ Specify where to find other target description files for inclusion. The
 F<directory> value should be a full or partial path to a directory that contains
 target description files.
 
+=item B<-asmparsernum> F<N>
+
+Make -gen-asm-parser emit assembly writer number F<N>.
+
 =item B<-asmwriternum> F<N>
 
 Make -gen-asm-writer emit assembly writer number F<N>.
@@ -57,27 +61,19 @@ Print all records to standard output (default).
 
 Print enumeration values for a class
 
+=item B<-print-sets>
+
+Print expanded sets for testing DAG exprs.
+
 =item B<-gen-emitter>
 
 Generate machine code emitter.
 
-=item B<-gen-register-enums>
+=item B<-gen-register-info>
 
-Generate the enumeration values for all registers.
+Generate registers and register classes info.
 
-=item B<-gen-register-desc>
-
-Generate a register info description for each register.
-
-=item B<-gen-register-desc-header>
-
-Generate a register info description header for each register.
-
-=item B<-gen-instr-enums>
-
-Generate enumeration values for instructions.
-
-=item B<-gen-instr-desc>
+=item B<-gen-instr-info>
 
 Generate instruction descriptions.
 
@@ -85,10 +81,30 @@ Generate instruction descriptions.
 
 Generate the assembly writer.
 
+=item B<-gen-disassembler>
+
+Generate disassembler.
+
+=item B<-gen-pseudo-lowering>
+
+Generate pseudo instruction lowering.
+
 =item B<-gen-dag-isel>
 
 Generate a DAG (Directed Acycle Graph) instruction selector.
 
+=item B<-gen-asm-matcher>
+
+Generate assembly instruction matcher.
+
+=item B<-gen-dfa-packetizer>
+
+Generate DFA Packetizer for VLIW targets.
+
+=item B<-gen-fast-isel>
+
+Generate a "fast" instruction selector.
+
 =item B<-gen-subtarget>
 
 Generate subtarget enumerations.
@@ -97,6 +113,14 @@ Generate subtarget enumerations.
 
 Generate intrinsic information.
 
+=item B<-gen-tgt-intrinsic>
+
+Generate target intrinsic information.
+
+=item B<-gen-enhanced-disassembly-info>
+
+Generate enhanced disassembly info.
+
 =item B<-version>
 
 Show the version number of this program.

utils/TableGen/CMakeLists.txt

@@ -22,7 +22,6 @@ add_tablegen(llvm-tblgen LLVM
   EDEmitter.cpp
   FastISelEmitter.cpp
   FixedLenDecoderEmitter.cpp
-  InstrEnumEmitter.cpp
   InstrInfoEmitter.cpp
   IntrinsicEmitter.cpp
   PseudoLoweringEmitter.cpp

utils/TableGen/InstrEnumEmitter.cpp

@@ -1,48 +0,0 @@
-//===- InstrEnumEmitter.cpp - Generate Instruction Set Enums --------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This tablegen backend is responsible for emitting enums for each machine
-// instruction.
-//
-//===----------------------------------------------------------------------===//
-
-#include "InstrEnumEmitter.h"
-#include "CodeGenTarget.h"
-#include "llvm/TableGen/Record.h"
-#include <cstdio>
-using namespace llvm;
-
-// runEnums - Print out enum values for all of the instructions.
-void InstrEnumEmitter::run(raw_ostream &OS) {
-  EmitSourceFileHeader("Target Instruction Enum Values", OS);
-  OS << "namespace llvm {\n\n";
-
-  CodeGenTarget Target(Records);
-
-  // We must emit the PHI opcode first...
-  std::string Namespace = Target.getInstNamespace();
-  
-  if (Namespace.empty()) {
-    fprintf(stderr, "No instructions defined!\n");
-    exit(1);
-  }
-
-  const std::vector<const CodeGenInstruction*> &NumberedInstructions =
-    Target.getInstructionsByEnumValue();
-
-  OS << "namespace " << Namespace << " {\n";
-  OS << "  enum {\n";
-  for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
-    OS << "    " << NumberedInstructions[i]->TheDef->getName()
-       << "\t= " << i << ",\n";
-  }
-  OS << "    INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n";
-  OS << "  };\n}\n";
-  OS << "} // End llvm namespace \n";
-}

utils/TableGen/InstrEnumEmitter.h

@@ -1,33 +0,0 @@
-//===- InstrEnumEmitter.h - Generate Instruction Set Enums ------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This tablegen backend is responsible for emitting enums for each machine
-// instruction.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef INSTRENUM_EMITTER_H
-#define INSTRENUM_EMITTER_H
-
-#include "llvm/TableGen/TableGenBackend.h"
-
-namespace llvm {
-
-class InstrEnumEmitter : public TableGenBackend {
-  RecordKeeper &Records;
-public:
-  InstrEnumEmitter(RecordKeeper &R) : Records(R) {}
-
-  // run - Output the instruction set description, returning true on failure.
-  void run(raw_ostream &OS);
-};
-
-} // End llvm namespace
-
-#endif