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Add instruction encodings / disassembler support for 2rus instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172985 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -137,6 +137,16 @@ static DecodeStatus Decode3RInstruction(MCInst &Inst,
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uint64_t Address,
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uint64_t Address,
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const void *Decoder);
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const void *Decoder);
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static DecodeStatus Decode2RUSInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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#include "XCoreGenDisassemblerTables.inc"
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#include "XCoreGenDisassemblerTables.inc"
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static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
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static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
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@ -202,6 +212,12 @@ Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
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// Try and decode as a 3R instruction.
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// Try and decode as a 3R instruction.
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unsigned Opcode = fieldFromInstruction(Insn, 11, 5);
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unsigned Opcode = fieldFromInstruction(Insn, 11, 5);
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switch (Opcode) {
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switch (Opcode) {
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case 0x0:
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Inst.setOpcode(XCore::STW_2rus);
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return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
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case 0x1:
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Inst.setOpcode(XCore::LDW_2rus);
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return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
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case 0x2:
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case 0x2:
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Inst.setOpcode(XCore::ADD_3r);
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Inst.setOpcode(XCore::ADD_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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@ -232,6 +248,21 @@ Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
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case 0x11:
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case 0x11:
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Inst.setOpcode(XCore::LD8U_3r);
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Inst.setOpcode(XCore::LD8U_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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case 0x12:
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Inst.setOpcode(XCore::ADD_2rus);
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return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
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case 0x13:
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Inst.setOpcode(XCore::SUB_2rus);
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return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
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case 0x14:
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Inst.setOpcode(XCore::SHL_2rus);
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return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
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case 0x15:
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Inst.setOpcode(XCore::SHR_2rus);
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return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
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case 0x16:
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Inst.setOpcode(XCore::EQ_2rus);
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return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
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case 0x18:
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case 0x18:
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Inst.setOpcode(XCore::LSS_3r);
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Inst.setOpcode(XCore::LSS_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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@ -361,6 +392,32 @@ Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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return S;
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return S;
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}
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}
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static DecodeStatus
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Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Op1, Op2, Op3;
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DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
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if (S == MCDisassembler::Success) {
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
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Inst.addOperand(MCOperand::CreateImm(Op3));
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}
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return S;
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}
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static DecodeStatus
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Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Op1, Op2, Op3;
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DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
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if (S == MCDisassembler::Success) {
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
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DecodeBitpOperand(Inst, Op3, Address, Decoder);
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}
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return S;
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}
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MCDisassembler::DecodeStatus
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MCDisassembler::DecodeStatus
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XCoreDisassembler::getInstruction(MCInst &instr,
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XCoreDisassembler::getInstruction(MCInst &instr,
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uint64_t &Size,
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uint64_t &Size,
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@ -43,8 +43,17 @@ class _FL3R<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<4, outs, ins, asmstr, pattern> {
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: InstXCore<4, outs, ins, asmstr, pattern> {
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}
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}
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class _F2RUS<dag outs, dag ins, string asmstr, list<dag> pattern>
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class _F2RUS<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<2, outs, ins, asmstr, pattern> {
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: InstXCore<2, outs, ins, asmstr, pattern> {
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let Inst{15-11} = opc;
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let DecoderMethod = "Decode2RUSInstruction";
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}
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// 2RUS with bitp operand
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class _F2RUSBitp<bits<5> opc, dag outs, dag ins, string asmstr,
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list<dag> pattern>
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: _F2RUS<opc, outs, ins, asmstr, pattern> {
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let DecoderMethod = "Decode2RUSBitpInstruction";
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}
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}
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class _FL2RUS<dag outs, dag ins, string asmstr, list<dag> pattern>
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class _FL2RUS<dag outs, dag ins, string asmstr, list<dag> pattern>
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@ -200,30 +200,30 @@ def InlineJT32 : Operand<i32> {
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// Three operand short
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// Three operand short
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multiclass F3R_2RUS<bits<5> opc, string OpcStr, SDNode OpNode> {
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multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
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def _3r: _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
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[(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
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def _2rus : _F2RUS<(outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
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def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
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[(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
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}
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}
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multiclass F3R_2RUS_np<bits<5> opc, string OpcStr> {
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multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> {
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def _3r: _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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!strconcat(OpcStr, " $dst, $b, $c"), []>;
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!strconcat(OpcStr, " $dst, $b, $c"), []>;
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def _2rus : _F2RUS<(outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
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def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
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!strconcat(OpcStr, " $dst, $b, $c"), []>;
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!strconcat(OpcStr, " $dst, $b, $c"), []>;
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}
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}
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multiclass F3R_2RBITP<bits<5> opc, string OpcStr, SDNode OpNode> {
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multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr,
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def _3r: _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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SDNode OpNode> {
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def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
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[(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
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def _2rus : _F2RUS<
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def _2rus : _F2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
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(outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
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[(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
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}
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}
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class F3R<bits<5> opc, string OpcStr, SDNode OpNode> :
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class F3R<bits<5> opc, string OpcStr, SDNode OpNode> :
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@ -382,10 +382,10 @@ let usesCustomInserter = 1 in {
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Three operand short
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// Three operand short
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defm ADD : F3R_2RUS<0b00010, "add", add>;
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defm ADD : F3R_2RUS<0b00010, 0b10010, "add", add>;
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defm SUB : F3R_2RUS<0b00011, "sub", sub>;
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defm SUB : F3R_2RUS<0b00011, 0b10011, "sub", sub>;
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let neverHasSideEffects = 1 in {
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let neverHasSideEffects = 1 in {
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defm EQ : F3R_2RUS_np<0b00110, "eq">;
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defm EQ : F3R_2RUS_np<0b00110, 0b10110, "eq">;
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def LSS_3r : F3R_np<0b11000, "lss">;
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def LSS_3r : F3R_np<0b11000, "lss">;
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def LSU_3r : F3R_np<0b11001, "lsu">;
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def LSU_3r : F3R_np<0b11001, "lsu">;
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}
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}
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@ -397,9 +397,9 @@ def LDW_3r : _F3R<0b01001, (outs GRRegs:$dst),
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(ins GRRegs:$addr, GRRegs:$offset),
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(ins GRRegs:$addr, GRRegs:$offset),
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"ldw $dst, $addr[$offset]", []>;
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"ldw $dst, $addr[$offset]", []>;
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def LDW_2rus : _F2RUS<(outs GRRegs:$dst), (ins GRRegs:$addr, i32imm:$offset),
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def LDW_2rus : _F2RUS<0b00001, (outs GRRegs:$dst),
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"ldw $dst, $addr[$offset]",
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(ins GRRegs:$addr, i32imm:$offset),
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[]>;
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"ldw $dst, $addr[$offset]", []>;
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def LD16S_3r : _F3R<0b10000, (outs GRRegs:$dst),
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def LD16S_3r : _F3R<0b10000, (outs GRRegs:$dst),
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(ins GRRegs:$addr, GRRegs:$offset),
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(ins GRRegs:$addr, GRRegs:$offset),
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@ -414,12 +414,13 @@ let mayStore=1 in {
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def STW_3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
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def STW_3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
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"stw $val, $addr[$offset]", []>;
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"stw $val, $addr[$offset]", []>;
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def STW_2rus : _F2RUS<(outs), (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset),
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def STW_2rus : _F2RUS<0b0000, (outs),
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"stw $val, $addr[$offset]", []>;
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(ins GRRegs:$val, GRRegs:$addr, i32imm:$offset),
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"stw $val, $addr[$offset]", []>;
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}
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}
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defm SHL : F3R_2RBITP<0b00100, "shl", shl>;
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defm SHL : F3R_2RBITP<0b00100, 0b10100, "shl", shl>;
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defm SHR : F3R_2RBITP<0b00101, "shr", srl>;
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defm SHR : F3R_2RBITP<0b00101, 0b10101, "shr", srl>;
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// TODO tsetr
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// TODO tsetr
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// Three operand long
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// Three operand long
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@ -234,3 +234,26 @@
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# CHECK: sub r4, r2, r5
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# CHECK: sub r4, r2, r5
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0x89 0x1a
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0x89 0x1a
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# 2rus instructions
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# CHECK: add r10, r2, 5
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0xe9 0x92
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# CHECK: eq r2, r1, 0
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0x24 0xb0
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# CHECK: ldw r5, r6[1]
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0x19 0x09
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# CHECK: shl r6, r5, 24
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0xa6 0xa5
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# CHECK: shr r3, r8, 5
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0xf1 0xab
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# CHECK: stw r3, r2[0]
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0x38 0x00
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# CHECK: sub r2, r4, 11
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0x63 0x9d
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