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Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern

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and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116432 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2010-10-13 21:00:04 +00:00
parent 67a704de03
commit b3af5de2d9
7 changed files with 33 additions and 19 deletions
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lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
+6 -2
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@@ -2998,13 +2998,17 @@ static bool DisassembleMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
case ARM::WFE:
case ARM::WFI:
case ARM::SEV:
case ARM::SETENDBE:
case ARM::SETENDLE:
return true;
default:
break;
}
if (Opcode == ARM::SETEND) {
NumOpsAdded = 1;
MI.addOperand(MCOperand::CreateImm(slice(insn, 9, 9)));
return true;
}
// CPS has a singleton $opt operand that contains the following information:
// opt{4-0} = mode from Inst{4-0}
// opt{5} = changemode from Inst{17}