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Add patterns for fround/fextend and the funny fsmuld instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24802 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -501,10 +501,12 @@ def FDTOI : F3_3<2, 0b110100, 0b011010010,
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// Convert between Floating-point Formats Instructions, p. 143
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def FSTOD : F3_3<2, 0b110100, 0b011001001,
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(ops DFPRegs:$dst, FPRegs:$src),
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"fstod $src, $dst", []>;
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"fstod $src, $dst",
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[(set DFPRegs:$dst, (fextend FPRegs:$src))]>;
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def FDTOS : F3_3<2, 0b110100, 0b011000110,
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(ops FPRegs:$dst, DFPRegs:$src),
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"fdtos $src, $dst", []>;
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"fdtos $src, $dst",
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[(set FPRegs:$dst, (fround DFPRegs:$src))]>;
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// Floating-point Move Instructions, p. 144
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def FMOVS : F3_3<2, 0b110100, 0b000000001,
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@ -546,11 +548,13 @@ def FMULD : F3_3<2, 0b110100, 0b001001010,
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[(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>;
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def FSMULD : F3_3<2, 0b110100, 0b001101001,
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(ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
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"fsmuld $src1, $src2, $dst", []>;
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"fsmuld $src1, $src2, $dst",
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[(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1),
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(fextend FPRegs:$src2)))]>;
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def FDIVS : F3_3<2, 0b110100, 0b001001101,
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(ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
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"fdivs $src1, $src2, $dst",
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[(set DFPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>;
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[(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>;
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def FDIVD : F3_3<2, 0b110100, 0b001001110,
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(ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
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"fdivd $src1, $src2, $dst",
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@ -501,10 +501,12 @@ def FDTOI : F3_3<2, 0b110100, 0b011010010,
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// Convert between Floating-point Formats Instructions, p. 143
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def FSTOD : F3_3<2, 0b110100, 0b011001001,
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(ops DFPRegs:$dst, FPRegs:$src),
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"fstod $src, $dst", []>;
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"fstod $src, $dst",
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[(set DFPRegs:$dst, (fextend FPRegs:$src))]>;
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def FDTOS : F3_3<2, 0b110100, 0b011000110,
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(ops FPRegs:$dst, DFPRegs:$src),
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"fdtos $src, $dst", []>;
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"fdtos $src, $dst",
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[(set FPRegs:$dst, (fround DFPRegs:$src))]>;
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// Floating-point Move Instructions, p. 144
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def FMOVS : F3_3<2, 0b110100, 0b000000001,
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@ -546,11 +548,13 @@ def FMULD : F3_3<2, 0b110100, 0b001001010,
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[(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>;
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def FSMULD : F3_3<2, 0b110100, 0b001101001,
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(ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
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"fsmuld $src1, $src2, $dst", []>;
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"fsmuld $src1, $src2, $dst",
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[(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1),
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(fextend FPRegs:$src2)))]>;
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def FDIVS : F3_3<2, 0b110100, 0b001001101,
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(ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
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"fdivs $src1, $src2, $dst",
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[(set DFPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>;
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[(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>;
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def FDIVD : F3_3<2, 0b110100, 0b001001110,
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(ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
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"fdivd $src1, $src2, $dst",
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