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[NVPTX] Add support for vectorized function return values
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185173 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1338,37 +1338,147 @@ SDValue NVPTXTargetLowering::LowerFormalArguments(
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}
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SDValue NVPTXTargetLowering::LowerReturn(
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SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals, SDLoc dl,
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SelectionDAG &DAG) const {
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SDValue
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NVPTXTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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SDLoc dl, SelectionDAG &DAG) const {
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MachineFunction &MF = DAG.getMachineFunction();
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const Function *F = MF.getFunction();
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const Type *RetTy = F->getReturnType();
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const DataLayout *TD = getDataLayout();
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bool isABI = (nvptxSubtarget.getSmVersion() >= 20);
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assert(isABI && "Non-ABI compilation is not supported");
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if (!isABI)
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return Chain;
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unsigned sizesofar = 0;
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unsigned idx = 0;
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for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
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SDValue theVal = OutVals[i];
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EVT theValType = theVal.getValueType();
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unsigned numElems = 1;
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if (theValType.isVector())
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numElems = theValType.getVectorNumElements();
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for (unsigned j = 0, je = numElems; j != je; ++j) {
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SDValue tmpval = theVal;
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if (const VectorType *VTy = dyn_cast<const VectorType>(RetTy)) {
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// If we have a vector type, the OutVals array will be the scalarized
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// components and we have combine them into 1 or more vector stores.
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unsigned NumElts = VTy->getNumElements();
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assert(NumElts == Outs.size() && "Bad scalarization of return value");
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// V1 store
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if (NumElts == 1) {
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SDValue StoreVal = OutVals[0];
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// We only have one element, so just directly store it
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if (StoreVal.getValueType().getSizeInBits() < 8)
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StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, StoreVal);
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Chain = DAG.getNode(NVPTXISD::StoreRetval, dl, MVT::Other, Chain,
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DAG.getConstant(0, MVT::i32), StoreVal);
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} else if (NumElts == 2) {
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// V2 store
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SDValue StoreVal0 = OutVals[0];
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SDValue StoreVal1 = OutVals[1];
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if (StoreVal0.getValueType().getSizeInBits() < 8) {
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StoreVal0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, StoreVal0);
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StoreVal1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, StoreVal1);
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}
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Chain = DAG.getNode(NVPTXISD::StoreRetvalV2, dl, MVT::Other, Chain,
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DAG.getConstant(0, MVT::i32), StoreVal0, StoreVal1);
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} else {
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// V4 stores
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// We have at least 4 elements (<3 x Ty> expands to 4 elements) and the
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// vector will be expanded to a power of 2 elements, so we know we can
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// always round up to the next multiple of 4 when creating the vector
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// stores.
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// e.g. 4 elem => 1 st.v4
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// 6 elem => 2 st.v4
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// 8 elem => 2 st.v4
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// 11 elem => 3 st.v4
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unsigned VecSize = 4;
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if (OutVals[0].getValueType().getSizeInBits() == 64)
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VecSize = 2;
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unsigned Offset = 0;
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EVT VecVT =
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EVT::getVectorVT(F->getContext(), OutVals[0].getValueType(), VecSize);
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unsigned PerStoreOffset =
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TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
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bool Extend = false;
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if (OutVals[0].getValueType().getSizeInBits() < 8)
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Extend = true;
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for (unsigned i = 0; i < NumElts; i += VecSize) {
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// Get values
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SDValue StoreVal;
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SmallVector<SDValue, 8> Ops;
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Ops.push_back(Chain);
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Ops.push_back(DAG.getConstant(Offset, MVT::i32));
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unsigned Opc = NVPTXISD::StoreRetvalV2;
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EVT ExtendedVT = (Extend) ? MVT::i8 : OutVals[0].getValueType();
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StoreVal = OutVals[i];
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if (Extend)
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StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, StoreVal);
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Ops.push_back(StoreVal);
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if (i + 1 < NumElts) {
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StoreVal = OutVals[i + 1];
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if (Extend)
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StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, StoreVal);
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} else {
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StoreVal = DAG.getUNDEF(ExtendedVT);
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}
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Ops.push_back(StoreVal);
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if (VecSize == 4) {
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Opc = NVPTXISD::StoreRetvalV4;
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if (i + 2 < NumElts) {
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StoreVal = OutVals[i + 2];
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if (Extend)
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StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, StoreVal);
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} else {
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StoreVal = DAG.getUNDEF(ExtendedVT);
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}
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Ops.push_back(StoreVal);
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if (i + 3 < NumElts) {
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StoreVal = OutVals[i + 3];
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if (Extend)
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StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, StoreVal);
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} else {
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StoreVal = DAG.getUNDEF(ExtendedVT);
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}
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Ops.push_back(StoreVal);
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}
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Chain = DAG.getNode(Opc, dl, MVT::Other, &Ops[0], Ops.size());
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Offset += PerStoreOffset;
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}
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}
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} else {
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unsigned sizesofar = 0;
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for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
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SDValue theVal = OutVals[i];
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EVT theValType = theVal.getValueType();
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unsigned numElems = 1;
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if (theValType.isVector())
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tmpval = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
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theValType.getVectorElementType(), tmpval,
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DAG.getIntPtrConstant(j));
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Chain = DAG.getNode(
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isABI ? NVPTXISD::StoreRetval : NVPTXISD::MoveToRetval, dl,
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MVT::Other, Chain, DAG.getConstant(isABI ? sizesofar : idx, MVT::i32),
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tmpval);
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if (theValType.isVector())
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sizesofar += theValType.getVectorElementType().getStoreSizeInBits() / 8;
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else
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sizesofar += theValType.getStoreSizeInBits() / 8;
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++idx;
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numElems = theValType.getVectorNumElements();
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for (unsigned j = 0, je = numElems; j != je; ++j) {
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SDValue tmpval = theVal;
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if (theValType.isVector())
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tmpval = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
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theValType.getVectorElementType(), tmpval,
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DAG.getIntPtrConstant(j));
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EVT theStoreType = tmpval.getValueType();
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if (theStoreType.getSizeInBits() < 8)
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tmpval = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, tmpval);
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Chain = DAG.getNode(NVPTXISD::StoreRetval, dl, MVT::Other, Chain,
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DAG.getConstant(sizesofar, MVT::i32), tmpval);
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if (theValType.isVector())
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sizesofar +=
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theValType.getVectorElementType().getStoreSizeInBits() / 8;
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else
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sizesofar += theValType.getStoreSizeInBits() / 8;
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}
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}
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}
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@ -23,3 +23,13 @@ define float @bar(<4 x float> %a) {
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%t4 = fadd float %t2, %t3
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ret float %t4
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}
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define <4 x float> @baz(<4 x float> %a) {
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; CHECK: .func (.param .align 16 .b8 func_retval0[16]) baz
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; CHECK: .param .align 16 .b8 baz_param_0[16]
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; CHECK: ld.param.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}
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; CHECK: st.param.v4.f32 [func_retval0+0], {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}
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%t1 = fmul <4 x float> %a, %a
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ret <4 x float> %t1
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}
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