mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-17 21:29:20 +00:00
* Minor cleanups
* Reduce number of #includes * Delete blank lines at end of files * Remove blatently misleading qualifiers (how do you have an inlined pure virtual function?) * Remove unnecesary & ignored qualifiers (const int argument vs int argument) * Remove LARGE chunks of "inline" code out to .cpp file * s/unsigned int/unsigned/ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1673 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
2182c785c2
commit
bc53c04789
@ -1,30 +1,17 @@
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// $Id$ -*-c++-*-
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//***************************************************************************
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// File:
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// MachineCacheInfo.h
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//
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// Purpose:
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// Describes properties of the target cache architecture.
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//**************************************************************************/
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//===-- llvm/Target/MachineCacheInfo.h ---------------------------*- C++ -*-==//
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//
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// Describes properties of the target cache architecture.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_MACHINECACHEINFO_H
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#define LLVM_TARGET_MACHINECACHEINFO_H
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#include "llvm/Target/TargetMachine.h"
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#include "Support/DataTypes.h"
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class TargetMachine;
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//---------------------------------------------------------------------------
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// class MachineCacheInfo
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//
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// Purpose:
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// Describes properties of the target cache architecture.
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//---------------------------------------------------------------------------
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class MachineCacheInfo : public NonCopyableV {
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public:
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const TargetMachine& target;
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struct MachineCacheInfo : public NonCopyableV {
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const TargetMachine ⌖
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protected:
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unsigned int numLevels;
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std::vector<unsigned short> cacheLineSizes;
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@ -32,8 +19,7 @@ protected:
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std::vector<unsigned short> cacheAssoc;
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public:
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/*ctor*/ MachineCacheInfo (const TargetMachine& tgt);
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/*dtor*/ virtual ~MachineCacheInfo () {}
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MachineCacheInfo(const TargetMachine& tgt);
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// Default parameters are:
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// NumLevels = 2
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@ -60,7 +46,4 @@ public:
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}
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};
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//---------------------------------------------------------------------------
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#endif
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@ -39,29 +39,22 @@ class BasicBlock;
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class MachineRegClassInfo {
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protected:
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const unsigned RegClassID; // integer ID of a reg class
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const unsigned NumOfAvailRegs; // # of avail for coloring -without SP etc.
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const unsigned NumOfAllRegs; // # of all registers -including SP,g0 etc.
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public:
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inline unsigned getRegClassID() const { return RegClassID; }
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inline unsigned getNumOfAvailRegs() const { return NumOfAvailRegs; }
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inline unsigned getNumOfAllRegs() const { return NumOfAllRegs; }
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// This method should find a color which is not used by neighbors
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// (i.e., a false position in IsColorUsedArr) and
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virtual void colorIGNode(IGNode * Node, bool IsColorUsedArr[] ) const = 0;
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virtual bool isRegVolatile(const int Reg) const = 0;
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MachineRegClassInfo(const unsigned ID, const unsigned NVR,
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const unsigned NAR): RegClassID(ID), NumOfAvailRegs(NVR),
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NumOfAllRegs(NAR)
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{ } // empty constructor
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virtual void colorIGNode(IGNode *Node, bool IsColorUsedArr[]) const = 0;
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virtual bool isRegVolatile(int Reg) const = 0;
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MachineRegClassInfo(unsigned ID, unsigned NVR, unsigned NAR)
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: RegClassID(ID), NumOfAvailRegs(NVR), NumOfAllRegs(NAR) {}
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};
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@ -74,27 +67,15 @@ public:
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//
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//--------------------------------------------------------------------------
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typedef std::hash_map<const MachineInstr *, AddedInstrns *> AddedInstrMapType;
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// A vector of all machine register classes
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//
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typedef std::vector<const MachineRegClassInfo *> MachineRegClassArrayType;
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class MachineRegInfo : public NonCopyableV {
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public:
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const TargetMachine& target;
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protected:
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MachineRegClassArrayType MachineRegClassArr;
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// A vector of all machine register classes
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//
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std::vector<const MachineRegClassInfo *> MachineRegClassArr;
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public:
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const TargetMachine ⌖
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// empty constructor
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//
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MachineRegInfo(const TargetMachine& tgt) : target(tgt) { }
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@ -103,7 +84,7 @@ public:
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// condition code register. If isCCReg is true below, the ID of the condition
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// code regiter class will be returned. Otherwise, the normal register
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// class (eg. int, float) must be returned.
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virtual unsigned getRegClassIDOfValue (const Value *const Val,
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virtual unsigned getRegClassIDOfValue (const Value *Val,
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bool isCCReg = false) const =0;
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@ -111,37 +92,37 @@ public:
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return MachineRegClassArr.size();
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}
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const MachineRegClassInfo *const getMachineRegClass(unsigned i) const {
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const MachineRegClassInfo *getMachineRegClass(unsigned i) const {
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return MachineRegClassArr[i];
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}
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// returns the register that is hardwired to zero if any (-1 if none)
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//
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virtual inline int getZeroRegNum() const = 0;
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virtual int getZeroRegNum() const = 0;
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// The following methods are used to color special live ranges (e.g.
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// method args and return values etc.) with specific hardware registers
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// as required. See SparcRegInfo.cpp for the implementation for Sparc.
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//
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virtual void suggestRegs4MethodArgs(const Method *const Meth,
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LiveRangeInfo & LRI) const = 0;
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virtual void suggestRegs4MethodArgs(const Method *Meth,
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LiveRangeInfo &LRI) const = 0;
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virtual void suggestRegs4CallArgs(const MachineInstr *const CallI,
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LiveRangeInfo& LRI, std::vector<RegClass *> RCL) const = 0;
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virtual void suggestRegs4CallArgs(const MachineInstr *CallI,
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LiveRangeInfo &LRI, std::vector<RegClass *> RCL) const = 0;
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virtual void suggestReg4RetValue(const MachineInstr *const RetI,
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LiveRangeInfo& LRI) const = 0;
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virtual void suggestReg4RetValue(const MachineInstr *RetI,
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LiveRangeInfo &LRI) const = 0;
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virtual void colorMethodArgs(const Method *const Meth, LiveRangeInfo& LRI,
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AddedInstrns *const FirstAI) const = 0;
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virtual void colorMethodArgs(const Method *Meth, LiveRangeInfo &LRI,
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AddedInstrns *FirstAI) const = 0;
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virtual void colorCallArgs(const MachineInstr *const CalI,
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LiveRangeInfo& LRI, AddedInstrns *const CallAI,
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virtual void colorCallArgs(const MachineInstr *CalI,
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LiveRangeInfo& LRI, AddedInstrns *CallAI,
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PhyRegAlloc &PRA, const BasicBlock *BB) const = 0;
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virtual void colorRetValue(const MachineInstr *const RetI,LiveRangeInfo& LRI,
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AddedInstrns *const RetAI) const = 0;
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virtual void colorRetValue(const MachineInstr *RetI, LiveRangeInfo &LRI,
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AddedInstrns *RetAI) const = 0;
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@ -150,21 +131,18 @@ public:
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// interface. However, they can be moved to MachineInstrInfo interface if
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// necessary.
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//
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virtual MachineInstr *
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cpReg2RegMI(const unsigned SrcReg, const unsigned DestReg,
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const int RegType) const=0;
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virtual MachineInstr *cpReg2RegMI(unsigned SrcReg, unsigned DestReg,
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int RegType) const = 0;
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virtual MachineInstr *
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cpReg2MemMI(const unsigned SrcReg, const unsigned DestPtrReg,
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const int Offset, const int RegType) const=0;
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virtual MachineInstr *cpReg2MemMI(unsigned SrcReg, unsigned DestPtrReg,
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int Offset, int RegType) const = 0;
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virtual MachineInstr *
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cpMem2RegMI(const unsigned SrcPtrReg, const int Offset,
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const unsigned DestReg, const int RegType) const=0;
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virtual MachineInstr *cpMem2RegMI(unsigned SrcPtrReg, int Offset,
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unsigned DestReg, int RegType) const = 0;
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virtual MachineInstr *cpValue2Value( Value *Src, Value *Dest) const=0;
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virtual MachineInstr *cpValue2Value(Value *Src, Value *Dest) const = 0;
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virtual bool isRegVolatile(const int RegClassID, const int Reg) const=0;
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virtual bool isRegVolatile(int RegClassID, int Reg) const = 0;
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@ -191,21 +169,21 @@ public:
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// Gives the type of a register based on the type of the LR
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//
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virtual int getRegType(const LiveRange *const LR) const=0;
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virtual int getRegType(const LiveRange *LR) const = 0;
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// Gives the return value contained in a CALL machine instruction
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//
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virtual const Value * getCallInstRetVal(const MachineInstr *CallMI) const=0;
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virtual const Value *getCallInstRetVal(const MachineInstr *CallMI) const = 0;
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// The following methods are used to get the frame/stack pointers
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//
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inline virtual unsigned getFramePointer() const=0;
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inline virtual unsigned getStackPointer() const=0;
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virtual unsigned getFramePointer() const = 0;
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virtual unsigned getStackPointer() const = 0;
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// A register can be initialized to an invalid number. That number can
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// be obtained using this method.
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//
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inline virtual int getInvalidRegNum() const=0;
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virtual int getInvalidRegNum() const = 0;
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// Method for inserting caller saving code. The caller must save all the
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@ -215,22 +193,12 @@ public:
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//
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virtual void insertCallerSavingCode(const MachineInstr *MInst,
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const BasicBlock *BB,
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PhyRegAlloc &PRA ) const = 0;
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PhyRegAlloc &PRA) const = 0;
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// This method gives the the number of bytes of stack spaceallocated
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// to a register when it is spilled to the stack.
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//
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virtual inline int getSpilledRegSize(const int RegType) const = 0;
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virtual int getSpilledRegSize(int RegType) const = 0;
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};
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#endif
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@ -1,4 +1,4 @@
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//===-- llvm/Target/SchedInfo.h - Target Instruction Sched Info --*- C++ -*-==//
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//===- Target/MachineSchedInfo.h - Target Instruction Sched Info -*- C++ -*-==//
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//
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// This file describes the target machine to the instruction scheduler.
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//
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@ -7,12 +7,12 @@
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#ifndef LLVM_TARGET_MACHINESCHEDINFO_H
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#define LLVM_TARGET_MACHINESCHEDINFO_H
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#include "llvm/Target/MachineInstrInfo.h"
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#include <ext/hash_map>
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#include "llvm/Target/MachineInstrInfo.h"
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typedef long long cycles_t;
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const cycles_t HUGE_LATENCY = ~((long long) 1 << (sizeof(cycles_t)-2));
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const cycles_t INVALID_LATENCY = -HUGE_LATENCY;
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static const cycles_t HUGE_LATENCY = ~((long long) 1 << (sizeof(cycles_t)-2));
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static const cycles_t INVALID_LATENCY = -HUGE_LATENCY;
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static const unsigned MAX_OPCODE_SIZE = 16;
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class OpCodePair {
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@ -29,11 +29,11 @@ private:
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};
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namespace std {
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template <> struct hash<OpCodePair> {
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size_t operator()(const OpCodePair& pair) const {
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return hash<long>()(pair.val);
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}
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};
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template <> struct hash<OpCodePair> {
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size_t operator()(const OpCodePair& pair) const {
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return hash<long>()(pair.val);
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}
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};
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}
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//---------------------------------------------------------------------------
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@ -46,15 +46,14 @@ template <> struct hash<OpCodePair> {
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//---------------------------------------------------------------------------
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typedef unsigned int resourceId_t;
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typedef unsigned resourceId_t;
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class MachineResource {
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public:
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struct MachineResource {
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const std::string rname;
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resourceId_t rid;
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/*ctor*/ MachineResource(const std::string& resourceName)
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: rname(resourceName), rid(nextId++) {}
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MachineResource(const std::string &resourceName)
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: rname(resourceName), rid(nextId++) {}
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private:
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static resourceId_t nextId;
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@ -62,12 +61,11 @@ private:
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};
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class CPUResource : public MachineResource {
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public:
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int maxNumUsers; // MAXINT if no restriction
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struct CPUResource : public MachineResource {
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int maxNumUsers; // MAXINT if no restriction
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/*ctor*/ CPUResource(const std::string& rname, int maxUsers)
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: MachineResource(rname), maxNumUsers(maxUsers) {}
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CPUResource(const std::string& rname, int maxUsers)
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: MachineResource(rname), maxNumUsers(maxUsers) {}
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};
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@ -96,30 +94,30 @@ struct InstrClassRUsage {
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int totCycles;
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// Issue restrictions common to instructions in this class
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unsigned int maxNumIssue;
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bool isSingleIssue;
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bool breaksGroup;
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cycles_t numBubbles;
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unsigned maxNumIssue;
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bool isSingleIssue;
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bool breaksGroup;
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cycles_t numBubbles;
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// Feasible slots to use for instructions in this class.
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// The size of vector S[] is `numSlots'.
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unsigned int numSlots;
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unsigned int feasibleSlots[MAX_NUM_SLOTS];
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unsigned numSlots;
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unsigned feasibleSlots[MAX_NUM_SLOTS];
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// Resource usages common to instructions in this class.
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// The size of vector V[] is `numRUEntries'.
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unsigned int numRUEntries;
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unsigned numRUEntries;
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struct {
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resourceId_t resourceId;
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unsigned int startCycle;
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int numCycles;
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} V[MAX_NUM_CYCLES];
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unsigned startCycle;
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int numCycles;
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} V[MAX_NUM_CYCLES];
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};
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struct InstrRUsageDelta {
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MachineOpCode opCode;
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resourceId_t resourceId;
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unsigned int startCycle;
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unsigned startCycle;
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int numCycles;
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};
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@ -135,10 +133,6 @@ struct InstrIssueDelta {
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struct InstrRUsage {
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/*ctor*/ InstrRUsage () {}
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/*ctor*/ InstrRUsage (const InstrRUsage& instrRU);
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InstrRUsage& operator= (const InstrRUsage& instrRU);
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bool sameAsClass;
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// Issue restrictions for this instruction
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@ -155,122 +149,24 @@ struct InstrRUsage {
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private:
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// Conveniences for initializing this structure
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InstrRUsage& operator= (const InstrClassRUsage& classRU);
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void addIssueDelta (const InstrIssueDelta& delta);
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void addUsageDelta (const InstrRUsageDelta& delta);
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void setMaxSlots (int maxNumSlots);
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void setTo(const InstrClassRUsage& classRU);
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void addIssueDelta(const InstrIssueDelta& delta) {
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sameAsClass = false;
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isSingleIssue = delta.isSingleIssue;
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breaksGroup = delta.breaksGroup;
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numBubbles = delta.numBubbles;
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}
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void addUsageDelta (const InstrRUsageDelta& delta);
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void setMaxSlots (int maxNumSlots) {
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feasibleSlots.resize(maxNumSlots);
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}
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friend class MachineSchedInfo; // give access to these functions
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};
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inline void
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InstrRUsage::setMaxSlots(int maxNumSlots)
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{
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feasibleSlots.resize(maxNumSlots);
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}
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inline InstrRUsage&
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InstrRUsage::operator=(const InstrRUsage& instrRU)
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{
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sameAsClass = instrRU.sameAsClass;
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isSingleIssue = instrRU.isSingleIssue;
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breaksGroup = instrRU.breaksGroup;
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numBubbles = instrRU.numBubbles;
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feasibleSlots = instrRU.feasibleSlots;
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numCycles = instrRU.numCycles;
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resourcesByCycle = instrRU.resourcesByCycle;
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return *this;
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}
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inline /*ctor*/
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InstrRUsage::InstrRUsage(const InstrRUsage& instrRU)
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{
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*this = instrRU;
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}
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inline InstrRUsage&
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InstrRUsage::operator=(const InstrClassRUsage& classRU)
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{
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sameAsClass = true;
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isSingleIssue = classRU.isSingleIssue;
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breaksGroup = classRU.breaksGroup;
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numBubbles = classRU.numBubbles;
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for (unsigned i=0; i < classRU.numSlots; i++)
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{
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unsigned slot = classRU.feasibleSlots[i];
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assert(slot < feasibleSlots.size() && "Invalid slot specified!");
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this->feasibleSlots[slot] = true;
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}
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|
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this->numCycles = classRU.totCycles;
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this->resourcesByCycle.resize(this->numCycles);
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for (unsigned i=0; i < classRU.numRUEntries; i++)
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for (unsigned c=classRU.V[i].startCycle, NC = c + classRU.V[i].numCycles;
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c < NC; c++)
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this->resourcesByCycle[c].push_back(classRU.V[i].resourceId);
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// Sort each resource usage vector by resourceId_t to speed up conflict checking
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for (unsigned i=0; i < this->resourcesByCycle.size(); i++)
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sort(resourcesByCycle[i].begin(), resourcesByCycle[i].end());
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|
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return *this;
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}
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|
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inline void
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InstrRUsage::addIssueDelta(const InstrIssueDelta& delta)
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{
|
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sameAsClass = false;
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isSingleIssue = delta.isSingleIssue;
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breaksGroup = delta.breaksGroup;
|
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numBubbles = delta.numBubbles;
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}
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|
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// Add the extra resource usage requirements specified in the delta.
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// Note that a negative value of `numCycles' means one entry for that
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// resource should be deleted for each cycle.
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//
|
||||
inline void
|
||||
InstrRUsage::addUsageDelta(const InstrRUsageDelta& delta)
|
||||
{
|
||||
int NC = delta.numCycles;
|
||||
|
||||
this->sameAsClass = false;
|
||||
|
||||
// resize the resources vector if more cycles are specified
|
||||
unsigned maxCycles = this->numCycles;
|
||||
maxCycles = std::max(maxCycles, delta.startCycle + abs(NC) - 1);
|
||||
if (maxCycles > this->numCycles)
|
||||
{
|
||||
this->resourcesByCycle.resize(maxCycles);
|
||||
this->numCycles = maxCycles;
|
||||
}
|
||||
|
||||
if (NC >= 0)
|
||||
for (unsigned c=delta.startCycle, last=c+NC-1; c <= last; c++)
|
||||
this->resourcesByCycle[c].push_back(delta.resourceId);
|
||||
else
|
||||
// Remove the resource from all NC cycles.
|
||||
for (unsigned c=delta.startCycle, last=(c-NC)-1; c <= last; c++)
|
||||
{
|
||||
// Look for the resource backwards so we remove the last entry
|
||||
// for that resource in each cycle.
|
||||
std::vector<resourceId_t>& rvec = this->resourcesByCycle[c];
|
||||
int r;
|
||||
for (r = (int) rvec.size(); r >= 0; r--)
|
||||
if (rvec[r] == delta.resourceId)
|
||||
{// found last entry for the resource
|
||||
rvec.erase(rvec.begin() + r);
|
||||
break;
|
||||
}
|
||||
assert(r >= 0 && "Resource to remove was unused in cycle c!");
|
||||
}
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// class MachineSchedInfo
|
||||
//
|
||||
@ -282,7 +178,7 @@ class MachineSchedInfo : public NonCopyableV {
|
||||
public:
|
||||
const TargetMachine& target;
|
||||
|
||||
unsigned int maxNumIssueTotal;
|
||||
unsigned maxNumIssueTotal;
|
||||
int longestIssueConflict;
|
||||
|
||||
int branchMispredictPenalty; // 4 for SPARC IIi
|
||||
@ -312,8 +208,8 @@ public:
|
||||
const InstrClassRUsage* _classRUsages,
|
||||
const InstrRUsageDelta* _usageDeltas,
|
||||
const InstrIssueDelta* _issueDeltas,
|
||||
unsigned int _numUsageDeltas,
|
||||
unsigned int _numIssueDeltas);
|
||||
unsigned _numUsageDeltas,
|
||||
unsigned _numIssueDeltas);
|
||||
/*dtor*/ virtual ~MachineSchedInfo () {}
|
||||
|
||||
inline const MachineInstrInfo& getInstrInfo() const {
|
||||
@ -324,11 +220,11 @@ public:
|
||||
return numSchedClasses;
|
||||
}
|
||||
|
||||
inline unsigned int getMaxNumIssueTotal() const {
|
||||
inline unsigned getMaxNumIssueTotal() const {
|
||||
return maxNumIssueTotal;
|
||||
}
|
||||
|
||||
inline unsigned int getMaxIssueForClass(const InstrSchedClass& sc) const {
|
||||
inline unsigned getMaxIssueForClass(const InstrSchedClass& sc) const {
|
||||
assert(sc >= 0 && sc < numSchedClasses);
|
||||
return classRUsages[sc].maxNumIssue;
|
||||
}
|
||||
@ -369,7 +265,7 @@ public:
|
||||
return getInstrRUsage(opCode).breaksGroup;
|
||||
}
|
||||
|
||||
inline unsigned int numBubblesAfter (MachineOpCode opCode) const {
|
||||
inline unsigned numBubblesAfter (MachineOpCode opCode) const {
|
||||
return getInstrRUsage(opCode).numBubbles;
|
||||
}
|
||||
|
||||
@ -386,8 +282,8 @@ protected:
|
||||
const InstrClassRUsage* classRUsages; // raw array by sclass
|
||||
const InstrRUsageDelta* usageDeltas; // raw array [1:numUsageDeltas]
|
||||
const InstrIssueDelta* issueDeltas; // raw array [1:numIssueDeltas]
|
||||
unsigned int numUsageDeltas;
|
||||
unsigned int numIssueDeltas;
|
||||
unsigned numUsageDeltas;
|
||||
unsigned numIssueDeltas;
|
||||
|
||||
std::vector<InstrRUsage> instrRUsages; // indexed by opcode
|
||||
std::hash_map<OpCodePair,int> issueGaps; // indexed by opcode pair
|
||||
|
||||
Loading…
Reference in New Issue
Block a user