mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
Move some dwarf emission routines to AsmPrinterDwarf.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203191 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher
parent
0e42ae9d8b
commit
d5c1fb9676
@ -16,7 +16,6 @@
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#include "DwarfDebug.h"
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#include "DwarfException.h"
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#include "WinCodeViewLineTables.h"
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#include "llvm/ADT/SmallBitVector.h"
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#include "llvm/ADT/SmallString.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Analysis/ConstantFolding.h"
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@ -872,161 +871,6 @@ void AsmPrinter::EmitFunctionBody() {
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OutStreamer.AddBlankLine();
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}
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/// Emit a dwarf register operation.
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static void emitDwarfRegOp(const AsmPrinter &AP, int Reg) {
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assert(Reg >= 0);
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if (Reg < 32) {
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AP.OutStreamer.AddComment(
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dwarf::OperationEncodingString(dwarf::DW_OP_reg0 + Reg));
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AP.EmitInt8(dwarf::DW_OP_reg0 + Reg);
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} else {
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AP.OutStreamer.AddComment("DW_OP_regx");
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AP.EmitInt8(dwarf::DW_OP_regx);
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AP.OutStreamer.AddComment(Twine(Reg));
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AP.EmitULEB128(Reg);
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}
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}
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/// Emit an (double-)indirect dwarf register operation.
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static void emitDwarfRegOpIndirect(const AsmPrinter &AP,
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int Reg, int Offset, bool Deref) {
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assert(Reg >= 0);
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if (Reg < 32) {
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AP.OutStreamer.AddComment(
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dwarf::OperationEncodingString(dwarf::DW_OP_breg0 + Reg));
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AP.EmitInt8(dwarf::DW_OP_breg0 + Reg);
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} else {
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AP.OutStreamer.AddComment("DW_OP_bregx");
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AP.EmitInt8(dwarf::DW_OP_bregx);
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AP.OutStreamer.AddComment(Twine(Reg));
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AP.EmitULEB128(Reg);
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}
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AP.EmitSLEB128(Offset);
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if (Deref)
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AP.EmitInt8(dwarf::DW_OP_deref);
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}
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/// Emit a dwarf register operation for describing
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/// - a small value occupying only part of a register or
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/// - a small register representing only part of a value.
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static void emitDwarfOpPiece(const AsmPrinter &AP,
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unsigned Size, unsigned Offset) {
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assert(Size > 0);
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if (Offset > 0) {
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AP.OutStreamer.AddComment("DW_OP_bit_piece");
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AP.EmitInt8(dwarf::DW_OP_bit_piece);
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AP.OutStreamer.AddComment(Twine(Size));
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AP.EmitULEB128(Size);
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AP.OutStreamer.AddComment(Twine(Offset));
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AP.EmitULEB128(Offset);
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} else {
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AP.OutStreamer.AddComment("DW_OP_piece");
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AP.EmitInt8(dwarf::DW_OP_piece);
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unsigned ByteSize = Size / 8; // Assuming 8 bits per byte.
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AP.OutStreamer.AddComment(Twine(ByteSize));
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AP.EmitULEB128(ByteSize);
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}
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}
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/// Some targets do not provide a DWARF register number for every
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/// register. This function attempts to emit a dwarf register by
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/// emitting a piece of a super-register or by piecing together
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/// multiple subregisters that alias the register.
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static void EmitDwarfRegOpPiece(const AsmPrinter &AP,
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const MachineLocation &MLoc) {
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assert(!MLoc.isIndirect());
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const TargetRegisterInfo *TRI = AP.TM.getRegisterInfo();
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int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false);
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// Walk up the super-register chain until we find a valid number.
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// For example, EAX on x86_64 is a 32-bit piece of RAX with offset 0.
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for (MCSuperRegIterator SR(MLoc.getReg(), TRI); SR.isValid(); ++SR) {
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Reg = TRI->getDwarfRegNum(*SR, false);
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if (Reg >= 0) {
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unsigned Idx = TRI->getSubRegIndex(*SR, MLoc.getReg());
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unsigned Size = TRI->getSubRegIdxSize(Idx);
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unsigned Offset = TRI->getSubRegIdxOffset(Idx);
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AP.OutStreamer.AddComment("super-register");
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emitDwarfRegOp(AP, Reg);
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emitDwarfOpPiece(AP, Size, Offset);
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return;
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}
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}
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// Otherwise, attempt to find a covering set of sub-register numbers.
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// For example, Q0 on ARM is a composition of D0+D1.
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//
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// Keep track of the current position so we can emit the more
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// efficient DW_OP_piece.
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unsigned CurPos = 0;
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// The size of the register in bits, assuming 8 bits per byte.
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unsigned RegSize = TRI->getMinimalPhysRegClass(MLoc.getReg())->getSize()*8;
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// Keep track of the bits in the register we already emitted, so we
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// can avoid emitting redundant aliasing subregs.
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SmallBitVector Coverage(RegSize, false);
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for (MCSubRegIterator SR(MLoc.getReg(), TRI); SR.isValid(); ++SR) {
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unsigned Idx = TRI->getSubRegIndex(MLoc.getReg(), *SR);
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unsigned Size = TRI->getSubRegIdxSize(Idx);
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unsigned Offset = TRI->getSubRegIdxOffset(Idx);
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Reg = TRI->getDwarfRegNum(*SR, false);
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// Intersection between the bits we already emitted and the bits
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// covered by this subregister.
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SmallBitVector Intersection(RegSize, false);
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Intersection.set(Offset, Offset+Size);
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Intersection ^= Coverage;
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// If this sub-register has a DWARF number and we haven't covered
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// its range, emit a DWARF piece for it.
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if (Reg >= 0 && Intersection.any()) {
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AP.OutStreamer.AddComment("sub-register");
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emitDwarfRegOp(AP, Reg);
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emitDwarfOpPiece(AP, Size, Offset == CurPos ? 0 : Offset);
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CurPos = Offset+Size;
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// Mark it as emitted.
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Coverage.set(Offset, Offset+Size);
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}
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}
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if (CurPos == 0) {
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// FIXME: We have no reasonable way of handling errors in here.
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AP.OutStreamer.AddComment("nop (could not find a dwarf register number)");
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AP.EmitInt8(dwarf::DW_OP_nop);
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}
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}
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/// EmitDwarfRegOp - Emit dwarf register operation.
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void AsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc,
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bool Indirect) const {
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const TargetRegisterInfo *TRI = TM.getRegisterInfo();
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int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false);
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if (Reg < 0) {
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// We assume that pointers are always in an addressable register.
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if (Indirect || MLoc.isIndirect()) {
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// FIXME: We have no reasonable way of handling errors in here. The
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// caller might be in the middle of a dwarf expression. We should
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// probably assert that Reg >= 0 once debug info generation is more
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// mature.
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OutStreamer.AddComment(
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"nop (invalid dwarf register number for indirect loc)");
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EmitInt8(dwarf::DW_OP_nop);
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return;
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}
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// Attempt to find a valid super- or sub-register.
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if (!Indirect && !MLoc.isIndirect())
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return EmitDwarfRegOpPiece(*this, MLoc);
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}
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if (MLoc.isIndirect())
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emitDwarfRegOpIndirect(*this, Reg, MLoc.getOffset(), Indirect);
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else if (Indirect)
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emitDwarfRegOpIndirect(*this, Reg, 0, false);
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else
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emitDwarfRegOp(*this, Reg);
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}
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bool AsmPrinter::doFinalization(Module &M) {
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// Emit global variables.
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for (Module::const_global_iterator I = M.global_begin(), E = M.global_end();
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@ -13,6 +13,7 @@
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#define DEBUG_TYPE "asm-printer"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/ADT/SmallBitVector.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/MC/MCAsmInfo.h"
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@ -183,6 +184,162 @@ void AsmPrinter::EmitSectionOffset(const MCSymbol *Label,
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EmitLabelDifference(Label, SectionLabel, 4);
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}
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/// Emit a dwarf register operation.
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static void emitDwarfRegOp(const AsmPrinter &AP, int Reg) {
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assert(Reg >= 0);
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if (Reg < 32) {
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AP.OutStreamer.AddComment(
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dwarf::OperationEncodingString(dwarf::DW_OP_reg0 + Reg));
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AP.EmitInt8(dwarf::DW_OP_reg0 + Reg);
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} else {
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AP.OutStreamer.AddComment("DW_OP_regx");
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AP.EmitInt8(dwarf::DW_OP_regx);
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AP.OutStreamer.AddComment(Twine(Reg));
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AP.EmitULEB128(Reg);
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}
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}
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/// Emit an (double-)indirect dwarf register operation.
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static void emitDwarfRegOpIndirect(const AsmPrinter &AP,
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int Reg, int Offset, bool Deref) {
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assert(Reg >= 0);
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if (Reg < 32) {
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AP.OutStreamer.AddComment(
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dwarf::OperationEncodingString(dwarf::DW_OP_breg0 + Reg));
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AP.EmitInt8(dwarf::DW_OP_breg0 + Reg);
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} else {
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AP.OutStreamer.AddComment("DW_OP_bregx");
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AP.EmitInt8(dwarf::DW_OP_bregx);
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AP.OutStreamer.AddComment(Twine(Reg));
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AP.EmitULEB128(Reg);
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}
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AP.EmitSLEB128(Offset);
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if (Deref)
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AP.EmitInt8(dwarf::DW_OP_deref);
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}
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/// Emit a dwarf register operation for describing
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/// - a small value occupying only part of a register or
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/// - a small register representing only part of a value.
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static void emitDwarfOpPiece(const AsmPrinter &AP,
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unsigned Size, unsigned Offset) {
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assert(Size > 0);
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if (Offset > 0) {
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AP.OutStreamer.AddComment("DW_OP_bit_piece");
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AP.EmitInt8(dwarf::DW_OP_bit_piece);
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AP.OutStreamer.AddComment(Twine(Size));
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AP.EmitULEB128(Size);
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AP.OutStreamer.AddComment(Twine(Offset));
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AP.EmitULEB128(Offset);
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} else {
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AP.OutStreamer.AddComment("DW_OP_piece");
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AP.EmitInt8(dwarf::DW_OP_piece);
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unsigned ByteSize = Size / 8; // Assuming 8 bits per byte.
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AP.OutStreamer.AddComment(Twine(ByteSize));
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AP.EmitULEB128(ByteSize);
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}
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}
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/// Some targets do not provide a DWARF register number for every
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/// register. This function attempts to emit a dwarf register by
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/// emitting a piece of a super-register or by piecing together
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/// multiple subregisters that alias the register.
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static void EmitDwarfRegOpPiece(const AsmPrinter &AP,
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const MachineLocation &MLoc) {
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assert(!MLoc.isIndirect());
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const TargetRegisterInfo *TRI = AP.TM.getRegisterInfo();
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int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false);
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// Walk up the super-register chain until we find a valid number.
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// For example, EAX on x86_64 is a 32-bit piece of RAX with offset 0.
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for (MCSuperRegIterator SR(MLoc.getReg(), TRI); SR.isValid(); ++SR) {
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Reg = TRI->getDwarfRegNum(*SR, false);
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if (Reg >= 0) {
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unsigned Idx = TRI->getSubRegIndex(*SR, MLoc.getReg());
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unsigned Size = TRI->getSubRegIdxSize(Idx);
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unsigned Offset = TRI->getSubRegIdxOffset(Idx);
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AP.OutStreamer.AddComment("super-register");
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emitDwarfRegOp(AP, Reg);
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emitDwarfOpPiece(AP, Size, Offset);
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return;
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}
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}
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// Otherwise, attempt to find a covering set of sub-register numbers.
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// For example, Q0 on ARM is a composition of D0+D1.
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//
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// Keep track of the current position so we can emit the more
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// efficient DW_OP_piece.
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unsigned CurPos = 0;
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// The size of the register in bits, assuming 8 bits per byte.
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unsigned RegSize = TRI->getMinimalPhysRegClass(MLoc.getReg())->getSize()*8;
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// Keep track of the bits in the register we already emitted, so we
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// can avoid emitting redundant aliasing subregs.
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SmallBitVector Coverage(RegSize, false);
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for (MCSubRegIterator SR(MLoc.getReg(), TRI); SR.isValid(); ++SR) {
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unsigned Idx = TRI->getSubRegIndex(MLoc.getReg(), *SR);
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unsigned Size = TRI->getSubRegIdxSize(Idx);
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unsigned Offset = TRI->getSubRegIdxOffset(Idx);
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Reg = TRI->getDwarfRegNum(*SR, false);
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// Intersection between the bits we already emitted and the bits
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// covered by this subregister.
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SmallBitVector Intersection(RegSize, false);
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Intersection.set(Offset, Offset+Size);
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Intersection ^= Coverage;
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// If this sub-register has a DWARF number and we haven't covered
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// its range, emit a DWARF piece for it.
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if (Reg >= 0 && Intersection.any()) {
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AP.OutStreamer.AddComment("sub-register");
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emitDwarfRegOp(AP, Reg);
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emitDwarfOpPiece(AP, Size, Offset == CurPos ? 0 : Offset);
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CurPos = Offset+Size;
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// Mark it as emitted.
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Coverage.set(Offset, Offset+Size);
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}
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}
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if (CurPos == 0) {
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// FIXME: We have no reasonable way of handling errors in here.
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AP.OutStreamer.AddComment("nop (could not find a dwarf register number)");
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AP.EmitInt8(dwarf::DW_OP_nop);
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}
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}
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/// EmitDwarfRegOp - Emit dwarf register operation.
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void AsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc,
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bool Indirect) const {
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const TargetRegisterInfo *TRI = TM.getRegisterInfo();
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int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false);
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if (Reg < 0) {
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// We assume that pointers are always in an addressable register.
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if (Indirect || MLoc.isIndirect()) {
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// FIXME: We have no reasonable way of handling errors in here. The
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// caller might be in the middle of a dwarf expression. We should
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// probably assert that Reg >= 0 once debug info generation is more
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// mature.
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OutStreamer.AddComment(
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"nop (invalid dwarf register number for indirect loc)");
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EmitInt8(dwarf::DW_OP_nop);
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return;
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}
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// Attempt to find a valid super- or sub-register.
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if (!Indirect && !MLoc.isIndirect())
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return EmitDwarfRegOpPiece(*this, MLoc);
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}
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if (MLoc.isIndirect())
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emitDwarfRegOpIndirect(*this, Reg, MLoc.getOffset(), Indirect);
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else if (Indirect)
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emitDwarfRegOpIndirect(*this, Reg, 0, false);
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else
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emitDwarfRegOp(*this, Reg);
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}
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//===----------------------------------------------------------------------===//
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// Dwarf Lowering Routines
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//===----------------------------------------------------------------------===//
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