mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-17 21:29:20 +00:00
Use MachineOperand::isFoo methods instead of our own global functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5033 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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8cbfc75d17
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d909683591
@ -200,11 +200,6 @@ void Emitter::emitMemModRMByte(const MachineInstr &MI,
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}
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}
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static bool isImmediate(const MachineOperand &MO) {
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return MO.getType() == MachineOperand::MO_SignExtendedImmed ||
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MO.getType() == MachineOperand::MO_UnextendedImmed;
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}
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unsigned sizeOfPtr (const MachineInstrDescriptor &Desc) {
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switch (Desc.TSFlags & X86II::ArgMask) {
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case X86II::Arg8: return 1;
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@ -276,12 +271,10 @@ void Emitter::emitInstruction(MachineInstr &MI) {
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emitRegModRMByte(MI.getOperand(0).getReg(),
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(Desc.TSFlags & X86II::FormMask)-X86II::MRMS0r);
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if (isImmediate(MI.getOperand(MI.getNumOperands()-1))) {
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if (MI.getOperand(MI.getNumOperands()-1).isImmediate()) {
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unsigned Size = sizeOfPtr(Desc);
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emitConstant(MI.getOperand(MI.getNumOperands()-1).getImmedValue(), Size);
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}
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break;
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}
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}
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@ -66,30 +66,16 @@ bool Printer::runOnFunction (Function & F)
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return false;
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}
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static bool isReg(const MachineOperand &MO) {
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return MO.getType() == MachineOperand::MO_VirtualRegister ||
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MO.getType() == MachineOperand::MO_MachineRegister;
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}
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static bool isImmediate(const MachineOperand &MO) {
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return MO.getType() == MachineOperand::MO_SignExtendedImmed ||
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MO.getType() == MachineOperand::MO_UnextendedImmed;
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}
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static bool isPCRelativeDisp(const MachineOperand &MO) {
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return MO.getType() == MachineOperand::MO_PCRelativeDisp;
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}
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static bool isScale(const MachineOperand &MO) {
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return isImmediate(MO) &&
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return MO.isImmediate() &&
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(MO.getImmedValue() == 1 || MO.getImmedValue() == 2 ||
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MO.getImmedValue() == 4 || MO.getImmedValue() == 8);
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}
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static bool isMem(const MachineInstr *MI, unsigned Op) {
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return Op+4 <= MI->getNumOperands() &&
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isReg(MI->getOperand(Op )) && isScale(MI->getOperand(Op+1)) &&
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isReg(MI->getOperand(Op+2)) && isImmediate(MI->getOperand(Op+3));
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MI->getOperand(Op ).isRegister() &&isScale(MI->getOperand(Op+1)) &&
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MI->getOperand(Op+2).isRegister() &&MI->getOperand(Op+3).isImmediate();
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}
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static void printOp(std::ostream &O, const MachineOperand &MO,
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@ -190,7 +176,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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// 2. jmp foo - PC relative displacement operand
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//
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assert(MI->getNumOperands() == 0 ||
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(MI->getNumOperands() == 1 && isPCRelativeDisp(MI->getOperand(0))) &&
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(MI->getNumOperands() == 1 && MI->getOperand(0).isPCRelativeDisp())&&
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"Illegal raw instruction!");
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O << getName(MI->getOpCode()) << " ";
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@ -208,11 +194,11 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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// an LLVM value, to represent, for example, loading the address of a global
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// into a register.
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//
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assert(isReg(MI->getOperand(0)) &&
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assert(MI->getOperand(0).isRegister() &&
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(MI->getNumOperands() == 1 ||
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(MI->getNumOperands() == 2 &&
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(MI->getOperand(1).getVRegValueOrNull() ||
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isImmediate(MI->getOperand(1))))) &&
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MI->getOperand(1).isImmediate()))) &&
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"Illegal form for AddRegFrm instruction!");
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unsigned Reg = MI->getOperand(0).getReg();
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@ -237,10 +223,10 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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//
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// 2 Operands: this is for things like mov that do not read a second input
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//
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assert(isReg(MI->getOperand(0)) &&
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assert(MI->getOperand(0).isRegister() &&
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(MI->getNumOperands() == 2 ||
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(MI->getNumOperands() == 3 && isReg(MI->getOperand(1)))) &&
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isReg(MI->getOperand(MI->getNumOperands()-1))
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(MI->getNumOperands() == 3 && MI->getOperand(1).isRegister())) &&
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MI->getOperand(MI->getNumOperands()-1).isRegister()
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&& "Bad format for MRMDestReg!");
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if (MI->getNumOperands() == 3 &&
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MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
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@ -259,7 +245,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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// register reference for the mod/rm field, it's a memory reference.
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//
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assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 &&
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isReg(MI->getOperand(4)) && "Bad format for MRMDestMem!");
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MI->getOperand(4).isRegister() && "Bad format for MRMDestMem!");
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O << getName(MI->getOpCode()) << " " << sizePtr (Desc) << " ";
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printMemReference(O, MI, 0, RI);
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@ -279,10 +265,10 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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//
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// 2 Operands: this is for things like mov that do not read a second input
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//
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assert(isReg(MI->getOperand(0)) &&
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isReg(MI->getOperand(1)) &&
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assert(MI->getOperand(0).isRegister() &&
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MI->getOperand(1).isRegister() &&
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(MI->getNumOperands() == 2 ||
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(MI->getNumOperands() == 3 && isReg(MI->getOperand(2))))
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(MI->getNumOperands() == 3 && MI->getOperand(2).isRegister()))
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&& "Bad format for MRMDestReg!");
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if (MI->getNumOperands() == 3 &&
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MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
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@ -300,9 +286,9 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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// These instructions are the same as MRMSrcReg, but instead of having a
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// register reference for the mod/rm field, it's a memory reference.
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//
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assert(isReg(MI->getOperand(0)) &&
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assert(MI->getOperand(0).isRegister() &&
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(MI->getNumOperands() == 1+4 && isMem(MI, 1)) ||
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(MI->getNumOperands() == 2+4 && isReg(MI->getOperand(1)) &&
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(MI->getNumOperands() == 2+4 && MI->getOperand(1).isRegister() &&
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isMem(MI, 2))
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&& "Bad format for MRMDestReg!");
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if (MI->getNumOperands() == 2+4 &&
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@ -328,21 +314,21 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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// 3. sbb rdest, rinput, immediate [rdest = rinput]
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//
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assert(MI->getNumOperands() > 0 && MI->getNumOperands() < 4 &&
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isReg(MI->getOperand(0)) && "Bad MRMSxR format!");
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MI->getOperand(0).isRegister() && "Bad MRMSxR format!");
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assert((MI->getNumOperands() != 2 ||
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isReg(MI->getOperand(1)) || isImmediate(MI->getOperand(1))) &&
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MI->getOperand(1).isRegister() || MI->getOperand(1).isImmediate())&&
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"Bad MRMSxR format!");
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assert((MI->getNumOperands() < 3 ||
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(isReg(MI->getOperand(1)) && isImmediate(MI->getOperand(2)))) &&
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(MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate())) &&
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"Bad MRMSxR format!");
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if (MI->getNumOperands() > 1 && isReg(MI->getOperand(1)) &&
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if (MI->getNumOperands() > 1 && MI->getOperand(1).isRegister() &&
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MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
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O << "**";
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O << getName(MI->getOpCode()) << " ";
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printOp(O, MI->getOperand(0), RI);
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if (isImmediate(MI->getOperand(MI->getNumOperands()-1))) {
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if (MI->getOperand(MI->getNumOperands()-1).isImmediate()) {
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O << ", ";
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printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
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}
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@ -66,30 +66,16 @@ bool Printer::runOnFunction (Function & F)
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return false;
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}
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static bool isReg(const MachineOperand &MO) {
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return MO.getType() == MachineOperand::MO_VirtualRegister ||
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MO.getType() == MachineOperand::MO_MachineRegister;
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}
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static bool isImmediate(const MachineOperand &MO) {
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return MO.getType() == MachineOperand::MO_SignExtendedImmed ||
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MO.getType() == MachineOperand::MO_UnextendedImmed;
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}
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static bool isPCRelativeDisp(const MachineOperand &MO) {
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return MO.getType() == MachineOperand::MO_PCRelativeDisp;
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}
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static bool isScale(const MachineOperand &MO) {
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return isImmediate(MO) &&
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return MO.isImmediate() &&
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(MO.getImmedValue() == 1 || MO.getImmedValue() == 2 ||
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MO.getImmedValue() == 4 || MO.getImmedValue() == 8);
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}
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static bool isMem(const MachineInstr *MI, unsigned Op) {
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return Op+4 <= MI->getNumOperands() &&
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isReg(MI->getOperand(Op )) && isScale(MI->getOperand(Op+1)) &&
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isReg(MI->getOperand(Op+2)) && isImmediate(MI->getOperand(Op+3));
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MI->getOperand(Op ).isRegister() &&isScale(MI->getOperand(Op+1)) &&
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MI->getOperand(Op+2).isRegister() &&MI->getOperand(Op+3).isImmediate();
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}
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static void printOp(std::ostream &O, const MachineOperand &MO,
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@ -190,7 +176,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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// 2. jmp foo - PC relative displacement operand
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//
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assert(MI->getNumOperands() == 0 ||
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(MI->getNumOperands() == 1 && isPCRelativeDisp(MI->getOperand(0))) &&
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(MI->getNumOperands() == 1 && MI->getOperand(0).isPCRelativeDisp())&&
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"Illegal raw instruction!");
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O << getName(MI->getOpCode()) << " ";
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@ -208,11 +194,11 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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// an LLVM value, to represent, for example, loading the address of a global
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// into a register.
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//
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assert(isReg(MI->getOperand(0)) &&
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assert(MI->getOperand(0).isRegister() &&
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(MI->getNumOperands() == 1 ||
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(MI->getNumOperands() == 2 &&
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(MI->getOperand(1).getVRegValueOrNull() ||
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isImmediate(MI->getOperand(1))))) &&
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MI->getOperand(1).isImmediate()))) &&
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"Illegal form for AddRegFrm instruction!");
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unsigned Reg = MI->getOperand(0).getReg();
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@ -237,10 +223,10 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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//
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// 2 Operands: this is for things like mov that do not read a second input
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//
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assert(isReg(MI->getOperand(0)) &&
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assert(MI->getOperand(0).isRegister() &&
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(MI->getNumOperands() == 2 ||
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(MI->getNumOperands() == 3 && isReg(MI->getOperand(1)))) &&
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isReg(MI->getOperand(MI->getNumOperands()-1))
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(MI->getNumOperands() == 3 && MI->getOperand(1).isRegister())) &&
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MI->getOperand(MI->getNumOperands()-1).isRegister()
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&& "Bad format for MRMDestReg!");
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if (MI->getNumOperands() == 3 &&
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MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
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@ -259,7 +245,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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// register reference for the mod/rm field, it's a memory reference.
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//
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assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 &&
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isReg(MI->getOperand(4)) && "Bad format for MRMDestMem!");
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MI->getOperand(4).isRegister() && "Bad format for MRMDestMem!");
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O << getName(MI->getOpCode()) << " " << sizePtr (Desc) << " ";
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printMemReference(O, MI, 0, RI);
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@ -279,10 +265,10 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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//
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// 2 Operands: this is for things like mov that do not read a second input
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//
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assert(isReg(MI->getOperand(0)) &&
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isReg(MI->getOperand(1)) &&
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assert(MI->getOperand(0).isRegister() &&
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MI->getOperand(1).isRegister() &&
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(MI->getNumOperands() == 2 ||
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(MI->getNumOperands() == 3 && isReg(MI->getOperand(2))))
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(MI->getNumOperands() == 3 && MI->getOperand(2).isRegister()))
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&& "Bad format for MRMDestReg!");
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if (MI->getNumOperands() == 3 &&
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MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
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@ -300,9 +286,9 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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// These instructions are the same as MRMSrcReg, but instead of having a
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// register reference for the mod/rm field, it's a memory reference.
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//
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assert(isReg(MI->getOperand(0)) &&
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assert(MI->getOperand(0).isRegister() &&
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(MI->getNumOperands() == 1+4 && isMem(MI, 1)) ||
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(MI->getNumOperands() == 2+4 && isReg(MI->getOperand(1)) &&
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(MI->getNumOperands() == 2+4 && MI->getOperand(1).isRegister() &&
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isMem(MI, 2))
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&& "Bad format for MRMDestReg!");
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if (MI->getNumOperands() == 2+4 &&
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@ -328,21 +314,21 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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// 3. sbb rdest, rinput, immediate [rdest = rinput]
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//
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assert(MI->getNumOperands() > 0 && MI->getNumOperands() < 4 &&
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isReg(MI->getOperand(0)) && "Bad MRMSxR format!");
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MI->getOperand(0).isRegister() && "Bad MRMSxR format!");
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assert((MI->getNumOperands() != 2 ||
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isReg(MI->getOperand(1)) || isImmediate(MI->getOperand(1))) &&
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MI->getOperand(1).isRegister() || MI->getOperand(1).isImmediate())&&
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"Bad MRMSxR format!");
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assert((MI->getNumOperands() < 3 ||
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(isReg(MI->getOperand(1)) && isImmediate(MI->getOperand(2)))) &&
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(MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate())) &&
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"Bad MRMSxR format!");
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if (MI->getNumOperands() > 1 && isReg(MI->getOperand(1)) &&
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if (MI->getNumOperands() > 1 && MI->getOperand(1).isRegister() &&
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MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
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O << "**";
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O << getName(MI->getOpCode()) << " ";
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printOp(O, MI->getOperand(0), RI);
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if (isImmediate(MI->getOperand(MI->getNumOperands()-1))) {
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if (MI->getOperand(MI->getNumOperands()-1).isImmediate()) {
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O << ", ";
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printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
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}
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@ -200,11 +200,6 @@ void Emitter::emitMemModRMByte(const MachineInstr &MI,
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}
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}
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static bool isImmediate(const MachineOperand &MO) {
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return MO.getType() == MachineOperand::MO_SignExtendedImmed ||
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MO.getType() == MachineOperand::MO_UnextendedImmed;
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}
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unsigned sizeOfPtr (const MachineInstrDescriptor &Desc) {
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switch (Desc.TSFlags & X86II::ArgMask) {
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case X86II::Arg8: return 1;
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@ -276,12 +271,10 @@ void Emitter::emitInstruction(MachineInstr &MI) {
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emitRegModRMByte(MI.getOperand(0).getReg(),
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(Desc.TSFlags & X86II::FormMask)-X86II::MRMS0r);
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if (isImmediate(MI.getOperand(MI.getNumOperands()-1))) {
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if (MI.getOperand(MI.getNumOperands()-1).isImmediate()) {
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unsigned Size = sizeOfPtr(Desc);
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emitConstant(MI.getOperand(MI.getNumOperands()-1).getImmedValue(), Size);
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}
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break;
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}
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}
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