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Some first bits of AltiVec stuff: Instruction Formats, Encodings, and
Registers. Apologies to Jim if the scheduling info so far isn't accurate. There's a few more things like VRsave support that need to be finished up in my local tree before I can commit code that Does The Right Thing for turning 4 x float into the various altivec packed float instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24489 91177308-0d34-0410-b5e6-96231b3b80d8
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Nate Begeman
parent
7c0c567058
commit
e4f17a5f9b
@ -548,6 +548,51 @@ class MDForm_1<bits<6> opcode, bits<3> xo, dag OL, string asmstr,
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let Inst{31} = RC;
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}
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// E-1 VA-Form
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class VAForm_1<bits<6> xo, dag OL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<4, OL, asmstr, itin> {
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bits<5> VD;
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bits<5> VA;
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bits<5> VB;
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bits<5> VC;
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let Inst{6-10} = VD;
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let Inst{11-15} = VA;
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let Inst{16-20} = VB;
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let Inst{21-25} = VC;
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let Inst{26-31} = xo;
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}
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// E-2 VX-Form
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class VXForm_1<bits<11> xo, dag OL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<4, OL, asmstr, itin> {
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bits<5> VD;
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bits<5> VA;
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bits<5> VB;
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let Inst{6-10} = VD;
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let Inst{11-15} = VA;
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let Inst{16-20} = VB;
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let Inst{21-31} = xo;
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}
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// E-4 VXR-Form
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class VXRForm_1<bits<10> xo, bit rc, dag OL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<4, OL, asmstr, itin> {
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bits<5> VD;
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bits<5> VA;
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bits<5> VB;
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let Inst{6-10} = VD;
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let Inst{11-15} = VA;
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let Inst{16-20} = VB;
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let Inst{21} = rc;
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let Inst{22-31} = xo;
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}
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//===----------------------------------------------------------------------===//
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def NoItin : InstrItinClass;
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class Pseudo<dag OL, string asmstr, list<dag> pattern>
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@ -360,6 +360,18 @@ def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
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"lwzx $dst, $base, $index", LdStGeneral>;
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def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
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"ldx $dst, $base, $index", LdStLD>, isPPC64;
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def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
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"lvebx $vD, $base, $rA", LdStGeneral>;
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def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
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"lvehx $vD, $base, $rA", LdStGeneral>;
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def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
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"lvewx $vD, $base, $rA", LdStGeneral>;
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def LVX : XForm_1<31, 103, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
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"lvx $vD, $base, $rA", LdStGeneral>;
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def LVSL : XForm_1<31, 6, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
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"lvsl $vD, $base, $rA", LdStGeneral>;
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def LVSR : XForm_1<31, 38, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
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"lvsl $vD, $base, $rA", LdStGeneral>;
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}
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def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"nand $rA, $rS, $rB", IntGeneral,
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@ -431,6 +443,14 @@ def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
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"stdx $rS, $rA, $rB", LdStSTD>, isPPC64;
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def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
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"stdux $rS, $rA, $rB", LdStSTD>, isPPC64;
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def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
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"stvebx $rS, $rA, $rB", LdStGeneral>;
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def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
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"stvehx $rS, $rA, $rB", LdStGeneral>;
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def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
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"stvewx $rS, $rA, $rB", LdStGeneral>;
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def STVX : XForm_8<31, 231, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
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"stvx $rS, $rA, $rB", LdStGeneral>;
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}
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def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
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"srawi $rA, $rS, $SH", IntShift,
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@ -746,6 +766,35 @@ def RLDICR : MDForm_1<30, 1,
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"rldicr $rA, $rS, $SH, $ME", IntRotateD,
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[]>, isPPC64;
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// VA-Form instructions. 3-input AltiVec ops.
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def VMADDFP: VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
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"vmaddfp $vD, $vA, $vB, $vC", VecFP,
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[]>;
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// VX-Form instructions. AltiVec arithmetic ops.
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def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vaddfp $vD, $vA, $vB", VecFP,
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[]>;
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def VADDUWM: VXForm_1<128, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vadduwm $vD, $vA, $vB", VecGeneral,
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[]>;
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def VAND : VXForm_1<1028, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vand $vD, $vA, $vB", VecGeneral,
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[]>;
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def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
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"vcfsx $vD, $vB, $UIMM", VecFP,
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[]>;
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def VCFUX : VXForm_1<778, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
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"vcfux $vD, $vB, $UIMM", VecFP,
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[]>;
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def VOR : VXForm_1<1156, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vor $vD, $vA, $vB", VecGeneral,
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[]>;
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def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vxor $vD, $vA, $vB", VecGeneral,
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[]>;
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//===----------------------------------------------------------------------===//
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// PowerPC Instruction Patterns
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//
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@ -37,6 +37,11 @@ class FPR<bits<5> num, string n> : PPCReg<n> {
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field bits<5> Num = num;
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}
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// VR - One of the 32 128-bit vector registers
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class VR<bits<5> num, string n> : PPCReg<n> {
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field bits<5> Num = num;
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}
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// CR - One of the 8 4-bit condition registers
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class CR<bits<5> num, string n> : PPCReg<n> {
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field bits<5> Num = num;
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@ -96,6 +101,23 @@ def F26 : FPR<26, "f26">; def F27 : FPR<27, "f27">;
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def F28 : FPR<28, "f28">; def F29 : FPR<29, "f29">;
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def F30 : FPR<30, "f30">; def F31 : FPR<31, "f31">;
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// Floating-point registers
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def V0 : VR< 0, "v0">; def V1 : VR< 1, "v1">;
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def V2 : VR< 2, "v2">; def V3 : VR< 3, "v3">;
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def V4 : VR< 4, "v4">; def V5 : VR< 5, "v5">;
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def V6 : VR< 6, "v6">; def V7 : VR< 7, "v7">;
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def V8 : VR< 8, "v8">; def V9 : VR< 9, "v9">;
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def V10 : VR<10, "v10">; def V11 : VR<11, "v11">;
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def V12 : VR<12, "v12">; def V13 : VR<13, "v13">;
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def V14 : VR<14, "v14">; def V15 : VR<15, "v15">;
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def V16 : VR<16, "v16">; def V17 : VR<17, "v17">;
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def V18 : VR<18, "v18">; def V19 : VR<19, "v19">;
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def V20 : VR<20, "v20">; def V21 : VR<21, "v21">;
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def V22 : VR<22, "v22">; def V23 : VR<23, "v23">;
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def V24 : VR<24, "v24">; def V25 : VR<25, "v25">;
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def V26 : VR<26, "v26">; def V27 : VR<27, "v27">;
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def V28 : VR<28, "v28">; def V29 : VR<29, "v29">;
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def V30 : VR<30, "v30">; def V31 : VR<31, "v31">;
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// Condition registers
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def CR0 : CR<0, "cr0">; def CR1 : CR<1, "cr1">;
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@ -104,9 +126,12 @@ def CR4 : CR<4, "cr4">; def CR5 : CR<5, "cr5">;
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def CR6 : CR<6, "cr6">; def CR7 : CR<7, "cr7">;
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// Link register
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def LR : SPR<2, "lr">;
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// FIXME: encode actual spr numbers here
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def LR : SPR<2, "lr">;
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// Count register
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def CTR : SPR<3, "ctr">;
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// VRsave register
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def VRSAVE: SPR<4, "VRsave">;
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/// Register classes
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// Allocate volatiles first
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@ -167,5 +192,8 @@ def F4RC : RegisterClass<"PPC", f32, 32, [F0, F1, F2, F3, F4, F5, F6, F7,
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F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
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F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
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def VRRC : RegisterClass<"PPC", i128, 128, [V0, V1, V2, V3, V4, V5, V6, V7, V8,
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V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, V21, V22, V23,
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V24, V25, V26, V27, V28, V29, V30, V31]>;
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def CRRC : RegisterClass<"PPC", i32, 32, [CR0, CR1, CR5, CR6, CR7, CR2, CR3, CR4]>;
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