mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-30 19:55:11 +00:00
Rewrite some ARM InstrInfo functions to be most accepting of arbitrary register subclasses. Hopefully this fixes some buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137223 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
parent
f5ade5d39a
commit
e66ef2d5f5
@ -711,82 +711,84 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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MFI.getObjectSize(FI),
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Align);
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// tGPR is used sometimes in ARM instructions that need to avoid using
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// certain registers. Just treat it as GPR here. Likewise, rGPR.
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if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass
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|| RC == ARM::rGPRRegisterClass)
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RC = ARM::GPRRegisterClass;
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switch (RC->getID()) {
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case ARM::GPRRegClassID:
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
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switch (RC->getSize()) {
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case 4:
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if (ARM::GPRRegClass.hasSubClassEq(RC)) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
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break;
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case ARM::SPRRegClassID:
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
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} else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
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break;
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case ARM::DPRRegClassID:
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case ARM::DPR_VFP2RegClassID:
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case ARM::DPR_8RegClassID:
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
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} else
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llvm_unreachable("Unknown reg class!");
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break;
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case 8:
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if (ARM::DPRRegClass.hasSubClassEq(RC)) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
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break;
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case ARM::QPRRegClassID:
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case ARM::QPR_VFP2RegClassID:
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case ARM::QPR_8RegClassID:
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if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo))
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} else
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llvm_unreachable("Unknown reg class!");
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break;
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case 16:
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if (ARM::QPRRegClass.hasSubClassEq(RC)) {
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if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo))
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.addFrameIndex(FI).addImm(16)
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.addReg(SrcReg, getKillRegState(isKill))
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.addMemOperand(MMO));
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} else {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
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} else {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI)
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.addMemOperand(MMO));
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}
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break;
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case ARM::QQPRRegClassID:
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case ARM::QQPR_VFP2RegClassID:
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if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
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// FIXME: It's possible to only store part of the QQ register if the
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// spilled def has a sub-register index.
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
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}
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} else
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llvm_unreachable("Unknown reg class!");
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break;
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case 32:
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if (ARM::QQPRRegClass.hasSubClassEq(RC)) {
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if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
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// FIXME: It's possible to only store part of the QQ register if the
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// spilled def has a sub-register index.
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
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.addFrameIndex(FI).addImm(16)
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.addReg(SrcReg, getKillRegState(isKill))
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.addMemOperand(MMO));
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} else {
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MachineInstrBuilder MIB =
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
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} else {
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MachineInstrBuilder MIB =
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
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.addFrameIndex(FI))
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.addMemOperand(MMO);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
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AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
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}
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break;
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case ARM::QQQQPRRegClassID: {
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MachineInstrBuilder MIB =
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
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.addFrameIndex(FI))
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.addMemOperand(MMO);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
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AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
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break;
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}
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default:
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llvm_unreachable("Unknown regclass!");
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.addMemOperand(MMO);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
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AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
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}
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} else
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llvm_unreachable("Unknown reg class!");
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break;
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case 64:
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if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
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MachineInstrBuilder MIB =
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
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.addFrameIndex(FI))
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.addMemOperand(MMO);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
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AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
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} else
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llvm_unreachable("Unknown reg class!");
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break;
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default:
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llvm_unreachable("Unknown reg class!");
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}
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}
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@ -860,72 +862,75 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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MFI.getObjectSize(FI),
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Align);
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// tGPR is used sometimes in ARM instructions that need to avoid using
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// certain registers. Just treat it as GPR here.
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if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass
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|| RC == ARM::rGPRRegisterClass)
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RC = ARM::GPRRegisterClass;
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switch (RC->getSize()) {
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case 4:
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if (ARM::GPRRegClass.hasSubClassEq(RC)) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
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switch (RC->getID()) {
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case ARM::GPRRegClassID:
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
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} else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
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} else
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llvm_unreachable("Unknown reg class!");
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break;
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case ARM::SPRRegClassID:
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
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case 8:
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if (ARM::DPRRegClass.hasSubClassEq(RC)) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
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} else
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llvm_unreachable("Unknown reg class!");
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break;
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case ARM::DPRRegClassID:
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case ARM::DPR_VFP2RegClassID:
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case ARM::DPR_8RegClassID:
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
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break;
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case ARM::QPRRegClassID:
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case ARM::QPR_VFP2RegClassID:
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case ARM::QPR_8RegClassID:
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if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg)
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case 16:
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if (ARM::QPRRegClass.hasSubClassEq(RC)) {
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if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg)
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.addFrameIndex(FI).addImm(16)
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.addMemOperand(MMO));
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} else {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
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.addFrameIndex(FI)
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.addMemOperand(MMO));
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}
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} else {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
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.addFrameIndex(FI)
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.addMemOperand(MMO));
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}
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} else
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llvm_unreachable("Unknown reg class!");
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break;
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case ARM::QQPRRegClassID:
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case ARM::QQPR_VFP2RegClassID:
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if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
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case 32:
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if (ARM::QQPRRegClass.hasSubClassEq(RC)) {
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if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
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.addFrameIndex(FI).addImm(16)
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.addMemOperand(MMO));
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} else {
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MachineInstrBuilder MIB =
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} else {
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MachineInstrBuilder MIB =
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
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.addFrameIndex(FI))
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.addMemOperand(MMO);
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.addMemOperand(MMO);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
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AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
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}
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} else
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llvm_unreachable("Unknown reg class!");
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break;
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case 64:
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if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
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MachineInstrBuilder MIB =
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
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.addFrameIndex(FI))
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.addMemOperand(MMO);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
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AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
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}
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MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI);
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AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);
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} else
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llvm_unreachable("Unknown reg class!");
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break;
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case ARM::QQQQPRRegClassID: {
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MachineInstrBuilder MIB =
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
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.addFrameIndex(FI))
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.addMemOperand(MMO);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI);
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AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);
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break;
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}
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default:
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llvm_unreachable("Unknown regclass!");
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}
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