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Eliminate operator[] is deprecated warnings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11578 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -53,9 +53,12 @@ struct ValueToDefVecMap: public hash_map<const Value*, RefVec> {
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SchedGraphNode::SchedGraphNode(unsigned NID, MachineBasicBlock *mbb,
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int indexInBB, const TargetMachine& Target)
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: SchedGraphNodeCommon(NID,indexInBB), MBB(mbb),
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MI(mbb ? &(*mbb)[indexInBB] : (MachineInstr*)0) {
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if (MI) {
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: SchedGraphNodeCommon(NID,indexInBB), MBB(mbb), MI(0) {
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if (mbb) {
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MachineBasicBlock::iterator I = MBB->begin();
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std::advance(I, indexInBB);
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MI = I;
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MachineOpCode mopCode = MI->getOpcode();
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latency = Target.getInstrInfo().hasResultInterlock(mopCode)
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? Target.getInstrInfo().minLatency(mopCode)
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@ -183,11 +186,11 @@ void SchedGraph::addCDEdges(const TerminatorInst* term,
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// Now add CD edges to the first branch instruction in the sequence from
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// all preceding instructions in the basic block. Use 0 latency again.
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//
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for (unsigned i=0, N=MBB.size(); i < N; i++) {
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if (&MBB[i] == termMvec[first]) // reached the first branch
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
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if (&*I == termMvec[first]) // reached the first branch
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break;
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SchedGraphNode* fromNode = this->getGraphNodeForInstr(&MBB[i]);
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SchedGraphNode* fromNode = getGraphNodeForInstr(I);
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if (fromNode == NULL)
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continue; // dummy instruction, e.g., PHI
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@ -199,11 +202,11 @@ void SchedGraph::addCDEdges(const TerminatorInst* term,
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// the terminator) that also have delay slots, add an outgoing edge
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// from the instruction to the instructions in the delay slots.
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//
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unsigned d = mii.getNumDelaySlots(MBB[i].getOpcode());
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assert(i+d < N && "Insufficient delay slots for instruction?");
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for (unsigned j=1; j <= d; j++) {
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SchedGraphNode* toNode = this->getGraphNodeForInstr(&MBB[i+j]);
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unsigned d = mii.getNumDelaySlots(I->getOpcode());
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MachineBasicBlock::iterator J = I; ++J;
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for (unsigned j=1; j <= d; j++, ++J) {
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SchedGraphNode* toNode = this->getGraphNodeForInstr(J);
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assert(toNode && "No node for machine instr in delay slot?");
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(void) new SchedGraphEdge(fromNode, toNode,
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SchedGraphEdge::CtrlDep,
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@ -554,10 +557,12 @@ void SchedGraph::buildNodesForBB(const TargetMachine& target,
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// Build graph nodes for each VM instruction and gather def/use info.
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// Do both those together in a single pass over all machine instructions.
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for (unsigned i=0; i < MBB.size(); i++)
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if (!mii.isDummyPhiInstr(MBB[i].getOpcode())) {
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unsigned i = 0;
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;
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++I, ++i)
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if (!mii.isDummyPhiInstr(I->getOpcode())) {
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SchedGraphNode* node = new SchedGraphNode(getNumNodes(), &MBB, i, target);
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noteGraphNodeForInstr(&MBB[i], node);
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noteGraphNodeForInstr(I, node);
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// Remember all register references and value defs
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findDefUseInfoAtInstr(target, node, memNodeVec, callDepNodeVec,
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@ -632,8 +637,8 @@ void SchedGraph::buildGraph(const TargetMachine& target) {
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this->addCallDepEdges(callDepNodeVec, target);
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// Then add incoming def-use (SSA) edges for each machine instruction.
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for (unsigned i=0, N=MBB.size(); i < N; i++)
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addEdgesForInstruction(MBB[i], valueToDefVecMap, target);
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I)
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addEdgesForInstruction(*I, valueToDefVecMap, target);
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// Then add edges for dependences on machine registers
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this->addMachineRegEdges(regToRefVecMap, target);
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@ -53,9 +53,12 @@ struct ValueToDefVecMap: public hash_map<const Value*, RefVec> {
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SchedGraphNode::SchedGraphNode(unsigned NID, MachineBasicBlock *mbb,
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int indexInBB, const TargetMachine& Target)
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: SchedGraphNodeCommon(NID,indexInBB), MBB(mbb),
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MI(mbb ? &(*mbb)[indexInBB] : (MachineInstr*)0) {
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if (MI) {
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: SchedGraphNodeCommon(NID,indexInBB), MBB(mbb), MI(0) {
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if (mbb) {
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MachineBasicBlock::iterator I = MBB->begin();
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std::advance(I, indexInBB);
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MI = I;
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MachineOpCode mopCode = MI->getOpcode();
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latency = Target.getInstrInfo().hasResultInterlock(mopCode)
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? Target.getInstrInfo().minLatency(mopCode)
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@ -183,11 +186,11 @@ void SchedGraph::addCDEdges(const TerminatorInst* term,
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// Now add CD edges to the first branch instruction in the sequence from
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// all preceding instructions in the basic block. Use 0 latency again.
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//
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for (unsigned i=0, N=MBB.size(); i < N; i++) {
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if (&MBB[i] == termMvec[first]) // reached the first branch
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
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if (&*I == termMvec[first]) // reached the first branch
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break;
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SchedGraphNode* fromNode = this->getGraphNodeForInstr(&MBB[i]);
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SchedGraphNode* fromNode = getGraphNodeForInstr(I);
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if (fromNode == NULL)
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continue; // dummy instruction, e.g., PHI
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@ -199,11 +202,11 @@ void SchedGraph::addCDEdges(const TerminatorInst* term,
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// the terminator) that also have delay slots, add an outgoing edge
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// from the instruction to the instructions in the delay slots.
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//
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unsigned d = mii.getNumDelaySlots(MBB[i].getOpcode());
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assert(i+d < N && "Insufficient delay slots for instruction?");
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for (unsigned j=1; j <= d; j++) {
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SchedGraphNode* toNode = this->getGraphNodeForInstr(&MBB[i+j]);
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unsigned d = mii.getNumDelaySlots(I->getOpcode());
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MachineBasicBlock::iterator J = I; ++J;
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for (unsigned j=1; j <= d; j++, ++J) {
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SchedGraphNode* toNode = this->getGraphNodeForInstr(J);
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assert(toNode && "No node for machine instr in delay slot?");
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(void) new SchedGraphEdge(fromNode, toNode,
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SchedGraphEdge::CtrlDep,
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@ -554,10 +557,12 @@ void SchedGraph::buildNodesForBB(const TargetMachine& target,
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// Build graph nodes for each VM instruction and gather def/use info.
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// Do both those together in a single pass over all machine instructions.
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for (unsigned i=0; i < MBB.size(); i++)
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if (!mii.isDummyPhiInstr(MBB[i].getOpcode())) {
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unsigned i = 0;
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;
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++I, ++i)
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if (!mii.isDummyPhiInstr(I->getOpcode())) {
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SchedGraphNode* node = new SchedGraphNode(getNumNodes(), &MBB, i, target);
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noteGraphNodeForInstr(&MBB[i], node);
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noteGraphNodeForInstr(I, node);
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// Remember all register references and value defs
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findDefUseInfoAtInstr(target, node, memNodeVec, callDepNodeVec,
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@ -632,8 +637,8 @@ void SchedGraph::buildGraph(const TargetMachine& target) {
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this->addCallDepEdges(callDepNodeVec, target);
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// Then add incoming def-use (SSA) edges for each machine instruction.
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for (unsigned i=0, N=MBB.size(); i < N; i++)
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addEdgesForInstruction(MBB[i], valueToDefVecMap, target);
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I)
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addEdgesForInstruction(*I, valueToDefVecMap, target);
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// Then add edges for dependences on machine registers
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this->addMachineRegEdges(regToRefVecMap, target);
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