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Eliminate operator[] is deprecated warnings

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11578 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2004-02-18 16:43:51 +00:00
parent fdc01cedd4
commit e6d04f1a99
2 changed files with 42 additions and 32 deletions
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35
lib/CodeGen/InstrSched/SchedGraph.cpp
View File

@@ -53,9 +53,12 @@ struct ValueToDefVecMap: public hash_map<const Value*, RefVec> {
SchedGraphNode::SchedGraphNode(unsigned NID, MachineBasicBlock *mbb, SchedGraphNode::SchedGraphNode(unsigned NID, MachineBasicBlock *mbb,
int indexInBB, const TargetMachine& Target) int indexInBB, const TargetMachine& Target)
: SchedGraphNodeCommon(NID,indexInBB), MBB(mbb), : SchedGraphNodeCommon(NID,indexInBB), MBB(mbb), MI(0) {
MI(mbb ? &(*mbb)[indexInBB] : (MachineInstr*)0) { if (mbb) {
if (MI) { MachineBasicBlock::iterator I = MBB->begin();
std::advance(I, indexInBB);
MI = I;
MachineOpCode mopCode = MI->getOpcode(); MachineOpCode mopCode = MI->getOpcode();
latency = Target.getInstrInfo().hasResultInterlock(mopCode) latency = Target.getInstrInfo().hasResultInterlock(mopCode)
? Target.getInstrInfo().minLatency(mopCode) ? Target.getInstrInfo().minLatency(mopCode)
@@ -183,11 +186,11 @@ void SchedGraph::addCDEdges(const TerminatorInst* term,
// Now add CD edges to the first branch instruction in the sequence from // Now add CD edges to the first branch instruction in the sequence from
// all preceding instructions in the basic block. Use 0 latency again. // all preceding instructions in the basic block. Use 0 latency again.
// //
for (unsigned i=0, N=MBB.size(); i < N; i++) { for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
if (&MBB[i] == termMvec[first]) // reached the first branch if (&*I == termMvec[first]) // reached the first branch
break; break;
SchedGraphNode* fromNode = this->getGraphNodeForInstr(&MBB[i]); SchedGraphNode* fromNode = getGraphNodeForInstr(I);
if (fromNode == NULL) if (fromNode == NULL)
continue; // dummy instruction, e.g., PHI continue; // dummy instruction, e.g., PHI
@@ -199,11 +202,11 @@ void SchedGraph::addCDEdges(const TerminatorInst* term,
// the terminator) that also have delay slots, add an outgoing edge // the terminator) that also have delay slots, add an outgoing edge
// from the instruction to the instructions in the delay slots. // from the instruction to the instructions in the delay slots.
// //
unsigned d = mii.getNumDelaySlots(MBB[i].getOpcode()); unsigned d = mii.getNumDelaySlots(I->getOpcode());
assert(i+d < N && "Insufficient delay slots for instruction?");
for (unsigned j=1; j <= d; j++) { MachineBasicBlock::iterator J = I; ++J;
SchedGraphNode* toNode = this->getGraphNodeForInstr(&MBB[i+j]); for (unsigned j=1; j <= d; j++, ++J) {
SchedGraphNode* toNode = this->getGraphNodeForInstr(J);
assert(toNode && "No node for machine instr in delay slot?"); assert(toNode && "No node for machine instr in delay slot?");
(void) new SchedGraphEdge(fromNode, toNode, (void) new SchedGraphEdge(fromNode, toNode,
SchedGraphEdge::CtrlDep, SchedGraphEdge::CtrlDep,
@@ -554,10 +557,12 @@ void SchedGraph::buildNodesForBB(const TargetMachine& target,
// Build graph nodes for each VM instruction and gather def/use info. // Build graph nodes for each VM instruction and gather def/use info.
// Do both those together in a single pass over all machine instructions. // Do both those together in a single pass over all machine instructions.
for (unsigned i=0; i < MBB.size(); i++) unsigned i = 0;
if (!mii.isDummyPhiInstr(MBB[i].getOpcode())) { for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;
++I, ++i)
if (!mii.isDummyPhiInstr(I->getOpcode())) {
SchedGraphNode* node = new SchedGraphNode(getNumNodes(), &MBB, i, target); SchedGraphNode* node = new SchedGraphNode(getNumNodes(), &MBB, i, target);
noteGraphNodeForInstr(&MBB[i], node); noteGraphNodeForInstr(I, node);
// Remember all register references and value defs // Remember all register references and value defs
findDefUseInfoAtInstr(target, node, memNodeVec, callDepNodeVec, findDefUseInfoAtInstr(target, node, memNodeVec, callDepNodeVec,
@@ -632,8 +637,8 @@ void SchedGraph::buildGraph(const TargetMachine& target) {
this->addCallDepEdges(callDepNodeVec, target); this->addCallDepEdges(callDepNodeVec, target);
// Then add incoming def-use (SSA) edges for each machine instruction. // Then add incoming def-use (SSA) edges for each machine instruction.
for (unsigned i=0, N=MBB.size(); i < N; i++) for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I)
addEdgesForInstruction(MBB[i], valueToDefVecMap, target); addEdgesForInstruction(*I, valueToDefVecMap, target);
// Then add edges for dependences on machine registers // Then add edges for dependences on machine registers
this->addMachineRegEdges(regToRefVecMap, target); this->addMachineRegEdges(regToRefVecMap, target);

35
lib/Target/SparcV9/InstrSched/SchedGraph.cpp
View File

@@ -53,9 +53,12 @@ struct ValueToDefVecMap: public hash_map<const Value*, RefVec> {
SchedGraphNode::SchedGraphNode(unsigned NID, MachineBasicBlock *mbb, SchedGraphNode::SchedGraphNode(unsigned NID, MachineBasicBlock *mbb,
int indexInBB, const TargetMachine& Target) int indexInBB, const TargetMachine& Target)
: SchedGraphNodeCommon(NID,indexInBB), MBB(mbb), : SchedGraphNodeCommon(NID,indexInBB), MBB(mbb), MI(0) {
MI(mbb ? &(*mbb)[indexInBB] : (MachineInstr*)0) { if (mbb) {
if (MI) { MachineBasicBlock::iterator I = MBB->begin();
std::advance(I, indexInBB);
MI = I;
MachineOpCode mopCode = MI->getOpcode(); MachineOpCode mopCode = MI->getOpcode();
latency = Target.getInstrInfo().hasResultInterlock(mopCode) latency = Target.getInstrInfo().hasResultInterlock(mopCode)
? Target.getInstrInfo().minLatency(mopCode) ? Target.getInstrInfo().minLatency(mopCode)
@@ -183,11 +186,11 @@ void SchedGraph::addCDEdges(const TerminatorInst* term,
// Now add CD edges to the first branch instruction in the sequence from // Now add CD edges to the first branch instruction in the sequence from
// all preceding instructions in the basic block. Use 0 latency again. // all preceding instructions in the basic block. Use 0 latency again.
// //
for (unsigned i=0, N=MBB.size(); i < N; i++) { for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
if (&MBB[i] == termMvec[first]) // reached the first branch if (&*I == termMvec[first]) // reached the first branch
break; break;
SchedGraphNode* fromNode = this->getGraphNodeForInstr(&MBB[i]); SchedGraphNode* fromNode = getGraphNodeForInstr(I);
if (fromNode == NULL) if (fromNode == NULL)
continue; // dummy instruction, e.g., PHI continue; // dummy instruction, e.g., PHI
@@ -199,11 +202,11 @@ void SchedGraph::addCDEdges(const TerminatorInst* term,
// the terminator) that also have delay slots, add an outgoing edge // the terminator) that also have delay slots, add an outgoing edge
// from the instruction to the instructions in the delay slots. // from the instruction to the instructions in the delay slots.
// //
unsigned d = mii.getNumDelaySlots(MBB[i].getOpcode()); unsigned d = mii.getNumDelaySlots(I->getOpcode());
assert(i+d < N && "Insufficient delay slots for instruction?");
for (unsigned j=1; j <= d; j++) { MachineBasicBlock::iterator J = I; ++J;
SchedGraphNode* toNode = this->getGraphNodeForInstr(&MBB[i+j]); for (unsigned j=1; j <= d; j++, ++J) {
SchedGraphNode* toNode = this->getGraphNodeForInstr(J);
assert(toNode && "No node for machine instr in delay slot?"); assert(toNode && "No node for machine instr in delay slot?");
(void) new SchedGraphEdge(fromNode, toNode, (void) new SchedGraphEdge(fromNode, toNode,
SchedGraphEdge::CtrlDep, SchedGraphEdge::CtrlDep,
@@ -554,10 +557,12 @@ void SchedGraph::buildNodesForBB(const TargetMachine& target,
// Build graph nodes for each VM instruction and gather def/use info. // Build graph nodes for each VM instruction and gather def/use info.
// Do both those together in a single pass over all machine instructions. // Do both those together in a single pass over all machine instructions.
for (unsigned i=0; i < MBB.size(); i++) unsigned i = 0;
if (!mii.isDummyPhiInstr(MBB[i].getOpcode())) { for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;
++I, ++i)
if (!mii.isDummyPhiInstr(I->getOpcode())) {
SchedGraphNode* node = new SchedGraphNode(getNumNodes(), &MBB, i, target); SchedGraphNode* node = new SchedGraphNode(getNumNodes(), &MBB, i, target);
noteGraphNodeForInstr(&MBB[i], node); noteGraphNodeForInstr(I, node);
// Remember all register references and value defs // Remember all register references and value defs
findDefUseInfoAtInstr(target, node, memNodeVec, callDepNodeVec, findDefUseInfoAtInstr(target, node, memNodeVec, callDepNodeVec,
@@ -632,8 +637,8 @@ void SchedGraph::buildGraph(const TargetMachine& target) {
this->addCallDepEdges(callDepNodeVec, target); this->addCallDepEdges(callDepNodeVec, target);
// Then add incoming def-use (SSA) edges for each machine instruction. // Then add incoming def-use (SSA) edges for each machine instruction.
for (unsigned i=0, N=MBB.size(); i < N; i++) for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I)
addEdgesForInstruction(MBB[i], valueToDefVecMap, target); addEdgesForInstruction(*I, valueToDefVecMap, target);
// Then add edges for dependences on machine registers // Then add edges for dependences on machine registers
this->addMachineRegEdges(regToRefVecMap, target); this->addMachineRegEdges(regToRefVecMap, target);