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Fix a CQ regression from my patch to split F32/F64 into seperate register

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classes on PPC.  We were emitting fmr instructions to do fp extensions, which
weren't getting coallesced.  This fixes Regression/CodeGen/PowerPC/fpcopy.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23654 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-10-07 05:00:52 +00:00
parent 602b02a8f4
commit eb5d47d99d
1 changed files with 2 additions and 1 deletions
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3
lib/Target/PowerPC/PPCInstrInfo.cpp
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@ -57,7 +57,8 @@ bool PPC32InstrInfo::isMoveInstr(const MachineInstr& MI,
destReg = MI.getOperand(0).getReg();
return true;
}
} else if (oc == PPC::FMRS || oc == PPC::FMRD) { // fmr r1, r2
} else if (oc == PPC::FMRS || oc == PPC::FMRD ||
oc == PPC::FMRSD) { // fmr r1, r2
assert(MI.getNumOperands() == 2 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&